High-resolution Analog-to-digital Converters Research Articles

Economic Modelling and Implementation of Test Signal Generator for Characterization of Continuous Time Sigma-Delta Analog-to-Digital Converter

Now there is a tremendous growth in the specific applications positively related to wireless communications, which posses the specific requirement for mixed-signal integrated circuits. When these independent circuits are used in the unique design of ADC and DAC practical applications, the considerable complexity of the testing increases. BIST is a precisely conventional technique which typically reduces this considerable complexity and prevents functional dependence on high-cost test equipment ATE. Moreover, in Built-In-self-Test (BIST), the output response analyzer (ORA) is the most significant component of architecture of continuous time (CT) sigma-delta analog-to-digital converter (ADC). There are numerous techniques of ORA used for accurate determining the design parameters like integral non-linearity (INL), differential non-linearity (DNL), signal-to-noise ratio (SNR). In this paper, the prime focus is primarily on the modern CORDIC technique which is used as ORA. For the modelling and accurate simulation of this technique Matlab simulink and CADENCE VIRTUOSO EDA tool environment software are properly implemented. A Coordinate Rotation Digital Computer (CORDIC) reduces the design complexity of the independent circuit. The design of ADC can be improved tremendously by typically using BIST. This paper focuses on the system level modelling of test stimuli generator (TSG) and its simulation for accurate characterization of high-resolution sigma-delta ADC. The successful implementation is carefully tested on Matlab simulink tool environment. The auto-testing external test equipment is required to test the integrated structures. TSG is implemented and it helps in extracting of statics and transmission parameters required for characterization of CT sigma-delta ADC.

A New Clock Phase Calibration Method in High-Speed and High-Resolution DACs

Current steering digital-to-analog converters (DACs) are well suited for high-resolution, high-speed applications. A serious design challenge is brought by the requirement of solving the setup/hold time violations problem between the output data from the digital clock domain and the analog clock under different process, voltage, and temperature conditions, and simultaneously maintaining high spectral purity of the analog clock. This brief presents a mixed-signal system to detect and correct setup/hold time violations for the critical analog clock in high-speed and high-resolution DACs. A power-efficient, novel 4-bit flash analog-to-digital converter, designed with a new architecture and reference adaptive generation technique while keeping overhead cost low, is proposed in this brief. The detection and correction circuit, together with a 13-bit 2.4-GHz DAC, is implemented in a 0.18- ${\mu }\text{m}$ CMOS technology. The measured spurious free dynamic range and the output spectrum demonstrate the effectiveness of the proposed method. The combined clock phase calibration circuit not only improves the yield of DAC, but also increases the maximum allowable clock frequency for high-resolution DACs, which is especially advantageous for high sampling frequency design.

Performance Analysis of Protograph LDPC Codes Over Large-Scale MIMO Channels With Low-Resolution ADCs

Protograph LDPC (P-LDPC) codes and large-scale multiple-input multiple-output (LS-MIMO) are cornerstones of 5G and future wireless systems, thanks to their powerful error-correcting capability and high spectral efficiency. To alleviate the high complexity in signal detection/decoding that dramatically grows with the number of antennas (in the order of tens or even hundreds), low-resolution analog-to-digital converters (ADCs) and joint detection and decoding using factor graph have recently attracted paramount interest. Unlike high-resolution ADCs, by using a small number of bits to quantize the received signal, low-resolution ADCs help reduce the hardware cost and power consumption of the RF circuit of practical LS-MIMO transceivers. Such a very much desirable reduction comes at the cost of additional quantization noise, introduced by low-resolution ADCs. This work aims to provide a unified framework to analyze the impact of the low-resolution ADCs on the performance of P-LDPC codes in practical LS-MIMO systems. It is worth noting that the previous analytical tools that have been used to evaluate the performance of P-LDPC codes do not account for the quantization noise effect of the low-resolution ADCs and the fact that the covariance of quantization noise depends on the fading channels. This article addresses this shortcoming by first leveraging the additive quantization noise model. We then derive the expression of extrinsic information for the belief-propagation LS-MIMO detector. The mutual information functions, which are the core elements of our proposed protograph extrinsic information transfer (PEXIT) algorithm, are analyzed for LS-MIMO communication systems. Our proposed PEXIT algorithm allows us to analyze and predict the impact of the low-resolution ADCs on the performance of P-LDPC codes, considering various input parameters, including the LS-MIMO configuration, the code rate, and the maximum number of decoding iterations, and the code structure. Based on our extensive analytical and simulation results, we found that the performance of 3-bit and 4-bit ADC systems only have a small gap to that of the unquantized systems. Especially when the 5-bit ADC scheme is applied, the performance loss is negligible. This finding sheds light on the practical design of LS-MIMO systems using P-LDPC codes.

A Biomedical Sensor System With Stochastic A/D Conversion and Error Correction by Machine Learning

This paper presents a high-precision biomedical sensor system with a novel analog-frontend (AFE) IC and error correction by machine learning. The AFE IC embeds an analog-to-digital converter (ADC) architecture called successive stochastic approximation ADC. The proposed ADC integrates a stochastic flash ADC (SF-ADC) into a successive approximation register ADC (SAR-ADC) to enhance its resolution. The SF-ADC is also used as a digitally controlled variable threshold comparator to provide error correction of the SAR-ADC. The proposed system also calibrates the ADC error using the machine learning algorithm on an external PC without additional power dissipation at a sensor node. Due to the flexibility of the system, the design complexity of an AFE IC can be relaxed by using these techniques. The target resolution is 18 bits, and the target bandwidth (without digital low-pass filter) is about 5 kHz to deal with several types of biopotential signals. The design is fabricated in a 130-nm CMOS process and operates at 1.2-V supply. The fabricated ADC achieves the SNDR of 88 dB at a sampling frequency of 250 kHz by using the proposed calibration techniques. Due to the high-resolution ADC, the input-referred noise is 2.52 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> with a gain of 28.5 dB.

Gridless Channel Estimation for Mixed One-Bit Antenna Array Systems

A receiver architecture with low-resolution analog-to-digital converters (ADCs) coupled with large antenna arrays has drawn considerable interest in the millimeter wave (mm-wave) system. Although architecture with pure one-bit ADCs has low power cost, such a system presents many challenges for synchronization, channel estimation, and power level estimation. Research has been conducted recently on the so-called mixed one-bit system, in which most antennas are equipped with one-bit ADCs, and a few have high-resolution ADCs. Despite the advantages of this system, studies on how to efficiently use high-resolution outputs to aid the one-bit system are lacking. This research considers the channel estimation problem to fill this gap and proposes a two-step channel estimator by utilizing the different features of mixed outputs. The channel gain can be extracted from high-resolution ADCs, and the channel angle can be extracted by the combination of additional one-bit ADCs. The proposed estimator leverages the sparsity feature of the channel in mm-wave. In contrast to previous works that used compressive sensing techniques, which confine the estimate to the set of grid angle points and induce estimation bias, the proposed estimator is gridless and treats the angle as a continuous parameter. The simulation results demonstrate that the proposed method yields significantly lower mean square errors than the conventional maximum likelihood estimator. In addition, this paper investigates ways to further improve the channel estimate by arranging the locations of high-resolution ADCs. Several useful observations on system design are obtained through our analysis.

A 15.2-ENOB 5-kHz BW 4.5-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;W Chopped CT &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\Delta\Sigma$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-ADC for Artifact-Tolerant Neural Recording Front Ends

Implantable closed-loop neural stimulation is desirable for clinical translation and basic neuroscience research. Neural stimulation generates large artifacts at the recording sites, which saturate existing recording front ends. This paper presents a low-power continuous-time delta-sigma analog to digital converter (ADC), which along with an 8 $\times $ gain capacitively-coupled chopper instrumentation amplifier (CCIA), realizes a front end that can digitize neural signals from 1 Hz to 5 kHz in the presence of 200-mVpp differential artifacts and 700-mVpp common-mode (CM) artifacts. A modified loop-filter is used in the ADC along with new linearization techniques to significantly reduce power consumption. Fabricated in 40-nm CMOS, the ADC occupies an area of 0.053 mm2, consumes 4.5 $\mu \text{W}$ from a 1.2-V supply, has an input impedance of 20 $\text{M}\Omega $ and bandwidth (BW) of 5 kHz, and achieves a peak signal to noise and distortion ratio (SNDR) of 93.5 dB for a 1.77- $\text{V}_{\mathrm {pp}}$ differential input at 1 kHz. The ADC’s figure of merit (FOM) (using SNDR) is 184 dB, which is 6 dB higher than the state of the art in high-resolution ADCs. The complete front end occupies an area of 0.113 mm2, consumes 7.3 $\mu \text{W}$ from a 1.2-V supply, has a dc input impedance of 1.5 $\text{G}\Omega $ , input-referred noise of 6.35 $\mu \text{V}_{\mathrm {rms}}$ in 1 Hz–5 kHz, and total harmonic distortion of −81 dB for a 200-mVpp input at 1 kHz, and is immune to 700-mVpp CM interference. Compared to front ends intended for closed-loop neural recording, this paper improves the linear input range by 2 $\times $ , the signal BW by 10 $\times $ , the dynamic range by 12.6 dB, the FOM by 12.4 dB and remains immune to large CM interference while maintaining comparable power, area, and noise performance.

Positive and Negative Feedback for Linearity Improvement and PVT Compensation of the Ramp Generator

Linearity of ramp signals is one of the most important aspects for many applications such as single-slope analog to digital converters (ADCs); another important aspect is the total power dissipation. Applications like high-resolution single-slope ADCs that can be used in portable devices demanded accurate ramp generator with low power dissipation. This paper presents a low power ramp generator with linearity improvement that achieved by a positive feedback circuit and negative feedback for compensation of the variations in process, voltage and temperature. Derived equations of the proposed ramp generator circuit show that linearity of the output ramp, with proper choosing of device sizes, can be enhanced significantly. Also, for proving of linearity enhancement, the circuit design and post-layout simulations were done in TSMC 0.18[Formula: see text][Formula: see text]m and 90[Formula: see text]nm CMOS technologies. Simulation results show that linearity of the circuit improved by a factor of 8 and total ramp resolution improved about 3 bit, whereas power dissipation of the circuit is about 8[Formula: see text][Formula: see text]W and entire layout core area is near 800[Formula: see text][Formula: see text]m2.

Comparator Design in Sensors for Environmental Monitoring

This paper presents circuit design considerations of comparator in analog-to-digital converters (ADC) applied for a portable, low-cost and high performance nano-sensor chip which can be applied to detect the airborne magnetite pollution nano particulate matter (PM) for environmental monitoring. High-resolution ADC plays a vital important role in high performance nano-sensor, while high-resolution comparator is a key component in ADC. In this work, some important design issues related to comparators in analog-to-digital converters (ADCs) are discussed, simulation results show that the resolution of the comparator proposed can achieve 5 µV, and it is appropriate for high-resolution application.

Bayesian Optimal Data Detector for Hybrid mmWave MIMO-OFDM Systems With Low-Resolution ADCs

Hybrid analog-digital precoding architectures and low-resolution analog-to-digital converter (ADC) receivers are two solutions to reduce hardware cost and power consumption for millimeter wave (mmWave) multiple-input multiple-output (MIMO) communication systems with large antenna arrays. In this study, we consider a mmWave MIMO-OFDM receiver with a generalized hybrid architecture in which a small number of radio-frequency (RF) chains and low-resolution ADCs are employed simultaneously. Owing to the strong nonlinearity introduced by low-resolution ADCs, the task of data detection is challenging, particularly achieving a Bayesian optimal data detector. This study aims to fill this gap. By using generalized expectation consistent signal recovery technique, we propose a computationally efficient data detection algorithm that provides a minimum mean-square error estimate on data symbols and is extended to a mixed-ADC architecture. Considering particular structure of MIMO-OFDM channel matirx, we provide a lowcomplexity realization in which only FFT operation and matrixvector multiplications are required. Furthermore, we present an analytical framework to study the theoretical performance of the detector in the large-system limit, which can precisely evaluate the performance expressions such as mean-square error and symbol error rate. Based on this optimal detector, the potential of adding a few low-resolution RF chains and high-resolution ADCs for mixed-ADC architecture is investigated. Simulation results confirm the accuracy of our theoretical analysis and can be used for system design rapidly. The results reveal that adding a few low-resolution RF chains to original unquantized systems can obtain significant gains.

Spectral Efficiency under Energy Constraint for Mixed-ADC MRC Massive MIMO

We consider uplink transmission for a massive multiuser multiple-input multiple-output (MU-MIMO) system in which the base station (BS) is equipped with a mixed analog-to-digital converter (ADC) architecture. In this architecture, a portion of the antennas at the BS is connected to low-power one-bit ADCs while the other is fed to power-hungry high-resolution ADCs. By taking into account the mixed-ADC architecture, we derive a closed-form expression for the sum spectral efficiency (SE) when maximum ratio combining (MRC) detection is employed at the BS. Then, we formulate an optimization problem to determine, for a given power budget at the BS, what is the optimal distribution of one-bit and high-resolution ADCs that maximizes the sum SE. Interestingly, it is shown that in most realistic scenarios, using only one-bit ADCs provides the best spectral efficiency for a given power budget constraint.

High-Precision, Mixed-Signal Mismatch Measurement of Metal–Oxide–Metal Capacitors

This brief presents a high-precision, mixed-signal mismatch measurement technique for metal–oxide–metal capacitors. The proposed technique incorporates a switched-capacitor op amp within the measurement circuit to significantly improve the measurement precision while relaxing the resolution requirement on the backend analog-to-digital converter (ADC). The proposed technique is also robust against multiple types of errors. A detailed analysis is presented to quantify the sensitivity improvement of the proposed technique over the conventional one. In addition, this brief proposes a multiplexing technique to measure a large number of capacitors in a single chip and a new layout to improve matching. A prototype fabricated in 180 nm technology demonstrates the ability to sense capacitor mismatch standard deviation as low as 0.045% with excellent repeatability, all without the need of a high-resolution ADC.

High-Resolution SAR ADC With Enhanced Linearity

This brief proposes two digital-to-analog converter switching techniques for binary-weighted capacitor array successive approximation register (SAR) analog-to-digital converter (ADC), rotating&averaging without redundancy technique and rotating&averaging with redundancy technique. The rotating&averaging without redundancy technique can improve the signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) of conventional SAR ADCs by averaging four samples for one input voltage, while the rotating&averaging with redundancy has better static linearity improvement but less SNR improvement than the rotating&averaging without redundancy technique. The application of these two methods to 14-bit SAR ADC is demonstrated by Monte-Carlo runs, results show that with a mismatch error typical of modern technology, the proposed rotating&averaging with redundancy scheme can improve the root-mean-square of integral nonlinearity from 2.08 to 0.57 LSB, and the SFDR is more than 15 dB better. On the other hand, the averaged SNR of 7.7 dB is improved by using the proposed rotating&averaging without redundancy technique for a 14-bit SAR ADC. Furthermore, the schemes proposed require only small additional circuit on a typical SAR ADC configuration, which are more feasible to implement high-resolution SAR ADC compared with the traditional calibration schemes.

High-resolution 1 MS/s sub-2 radix split-capacitor SAR ADC

This paper proposes a high-resolution successive-approximation register (SAR) analog-to-digital converter (ADC) with sub-2 radix split-capacitor array architecture. The built-in redundancy of sub-2 radix architecture provides additional information in the digital calibration based on offset double injection. The calibration method is simple in structure and fast in convergence. The correction of errors in each bit is independent of those in the previous bit. A split-capacitor array is used to reduce the total capacitance especially in a high-resolution SAR ADC. An offset signal is injected by the switching scheme of capacitor array to minimize the hardware overhead. The prototype of 0.18 μm CMOS process obtains 14.46 bit ENOB and 95.65 dB SFDR after calibration. With calibration, the INL and DNL are −0.813/0.938 and −0.625/0.688, respectively.

1-bit Observation for Direct-Learning-Based Digital Predistortion of RF Power Amplifiers

In this paper, we propose a low-cost data-acquisition approach for model extraction of digital predistortion (DPD) of RF power amplifiers. The proposed approach utilizes only 1-bit-resolution analog-to-digital converters (ADCs) in the observation path to digitize the error signal between the input and output signals. The DPD coefficients are then estimated based on the direct learning architecture using the measured signs of the error signal. The proposed solution is proved feasible in theory, and the experimental results show that the proposed algorithm achieves the performance equivalent to that using the conventional method. Replacing high-resolution ADCs with 1-bit comparators in the feedback path can dramatically reduce the power consumption and cost of the DPD system. The 1-bit solution also makes DPD become practically implementable in future broadband systems since it is relatively straightforward to achieve an ultrahigh sampling speed in data conversion using only simple comparators.

Performance Analysis of Mixed-ADC Massive MIMO Systems Over Rician Fading Channels

The practical deployment of massive multiple-input multiple-output (MIMO) in future fifth generation (5G) wireless communication systems is challenging due to its high hardware cost and power consumption. One promising solution to address this challenge is to adopt the low-resolution analog-to-digital converter (ADC) architecture. However, the practical implementation of such architecture is challenging due to the required complex signal processing to compensate the coarse quantization caused by low-resolution ADCs. Therefore, few high-resolution ADCs are reserved in the recently proposed mixed-ADC architecture to enable low-complexity transceiver algorithms. In contrast to previous works over Rayleigh fading channels, we investigate the performance of mixed-ADC massive MIMO systems over the Rician fading channel, which is more general for the 5G scenarios like Internet of Things (IoT). Specially, novel closed-form approximate expressions for the uplink achievable rate are derived for both cases of perfect and imperfect channel state information (CSI). With the increasing Rician $K$-factor, the derived results show that the achievable rate will converge to a fixed value. We also obtain the power-scaling law that the transmit power of each user can be scaled down proportionally to the inverse of the number of base station (BS) antennas for both perfect and imperfect CSI. Moreover, we reveal the trade-off between the achievable rate and energy efficiency with respect to key system parameters including the quantization bits, number of BS antennas, Rician $K$-factor, user transmit power, and CSI quality. Finally, numerical results are provided to show that the mixed-ADC architecture can achieve a better energy-rate trade-off compared with the ideal infinite-resolution and low-resolution ADC architectures.

Effective method to improve linearity of high-resolution SAR ADC

This work proposes one DAC switching technique for successive approximation register (SAR) analog-to-digital converter (ADC), cycling&averaging technique. The proposed cycling&averaging technique can reduce the noise and harmonic distortion caused by capacitor mismatch without trimming or complicated least-mean-square(LMS) digital calibration. The application of the cycling&averaging technique to two kinds of 12-bit SAR ADC is demonstrated by 1000 Monte-Carlo runs, in which the capacitor mismatch for every capacitor is randomly generated for one thousand times. Simulation results show that the method improves the differential non-linearity (DNL) from 1.45 LSB to 0.47 LSB and the integral non-linearity (INL) from 1.87 LSB to 0.48 LSB with a standard deviation of 4%. Further, the SFDR is more than 10dB better. Meanwhile, the schemes proposed require only small additional circuit on a typical SAR ADC configuration, which are more feasible to implement high-resolution SAR ADC compared with the traditional calibration schemes.

Mixed-ADC Massive MIMO

Motivated by the demand for energy-efficient communication solutions in the next generation cellular network, a mixed-ADC architecture for massive multiple input multiple output (MIMO) systems is proposed, which differs from previous works in that herein one-bit analog-to-digital converters (ADCs) partially replace the conventionally assumed high-resolution ADCs. The information-theoretic tool of generalized mutual information (GMI) is exploited to analyze the achievable data rates of the proposed system architecture and an array of analytical results of engineering interest are obtained. For fixed single input multiple output (SIMO) channels, a closed-form expression of the GMI is derived, based on which the linear combiner is optimized. The analysis is then extended to ergodic fading channels, for which tight lower and upper bounds of the GMI are obtained. Impacts of dithering and imperfect channel state information (CSI) are also investigated, and it is shown that dithering can remarkably improve the system performance while imperfect CSI only introduces a marginal rate loss. Finally, the analytical framework is applied to the multi-user access scenario. Numerical results demonstrate that the mixed-ADC architecture with a relatively small number of high-resolution ADCs is able to achieve a large fraction of the channel capacity of conventional architecture, while reduce the energy consumption considerably even compared with antenna selection, for both single-user and multi-user scenarios.

Optimal Design of Secrecy Massive MIMO Amplify-and-Forward Relaying Systems With Double-Resolution ADCs Antenna Array

This paper focuses on a secrecy constrained massive multiple-input multiple-output (MIMO) relaying system in terms of the optimal design of system parameters such as the optimal total number of antennas at relay, where a more practical mixed analog-to-digital converters (ADCs) scheme, double-resolution ADCs scheme, is proposed. In the proposed double-resolution ADCs scheme, the total $M$ antennas at relay are divided into two parts, one of which includes $M_{0}$ antennas with medium-resolution ADCs only requiring 5~12 quantization bits and the remainder of which consists of $M_{1}$ antennas with low-resolution ADCs. The transmission from relay to destinations is exposed to a passive eavesdropper. For such massive MIMO relaying systems, we first derive the total achievable ergodic rates of legitimate users as well as the corresponding secrecy outage rates. Then, a reasonable energy consumption model is modeled so that the secrecy energy efficiency (SEE) is derived, where the effect of the source power, the resolutions of ADCs, and the ratio of the antenna numbers with medium- and low-resolution ADCs are exploited perfectly. The presented numerical results show that replacing high-resolution ADCs with medium-resolution ADCs is beneficial for improving the system SEE while the effect on the total achievable rate is very small. Specially, three main insights are achieved: 1) there exists an optimal value of the source power at which the SEE is optimal; 2) with given ratio $M_{0} :M_{1} $ , the optimal value of quantization bits of medium-resolution ADCs is upper-bounded, under which the system has higher SEE, that is to say, we obtain the upper bound of the resolution of the medium-resolution ADCs; and 3) the optimal number of the total antennas is impacted jointly by the number $b_{0}$ of the quantization bits of medium-resolution ADCs and the ratio $M_{0} :M_{1}$ . Specially, while the optimal number of the total antennas is 100 or so for the pure high-resolution ADCs systems, the one for the proposed double-resolution ADCs systems would up to 500~700. Moreover, the optimal antenna number is increasing with the decrease of $b_{0} $ and the ratio $M_{0} :M_{1} $ so that the system performance can be improved further.

A 1.1-Gbit/s 10-GHz Outphasing Modulator With 23-dBm Output Power and 60-dB Dynamic Range in 45-nm CMOS SOI

A 10-GHz outphasing modulator is implemented in a 45-nm CMOS silicon-on-insulator process. The modulator is designed to provide high linearity and can operate at high data rates by using 256-QAM while maintaining low error vector magnitude (EVM). Four high-speed 10-bit digital-to-analog converters (DACs) are integrated with dual in-phase and quadrature upconverters. To deliver high output power to an off-chip power amplifier, stacked field-effect transistor current buffers are used to isolate the modulator from the load and mitigate device breakdown. As a result, this modulator delivers 23 dBm to a differential 100- $\Omega$ load. The high-resolution DACs provide a fine control of the phase between the outphased signals and support more than 60 dB of dynamic range and power steps smaller than 1 dB over the entire output power range. The outphasing modulator demonstrates an EVM of 2.2% at 80 Mbit/s and an EVM of 3.4% at 1.1 Gbit/s for 256-QAM. To our knowledge, this is the first demonstration of an outphasing modulator operating above 1 Gb/s.

Histogram-Based Calibration Method for Pipeline ADCs.

Measurement and calibration of an analog-to-digital converter (ADC) using a histogram-based method requires a large volume of data and a long test duration, especially for a high resolution ADC. A fast and accurate calibration method for pipelined ADCs is proposed in this research. The proposed calibration method composes histograms through the outputs of each stage and calculates error sources. The digitized outputs of a stage are influenced directly by the operation of the prior stage, so the results of the histogram provide the information of errors in the prior stage. The composed histograms reduce the required samples and thus calibration time being implemented by simple modules. For 14-bit resolution pipelined ADC, the measured maximum integral non-linearity (INL) is improved from 6.78 to 0.52 LSB, and the spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are improved from 67.0 to 106.2dB and from 65.6 to 84.8dB, respectively.