High-resistivity Substrate Research Articles

CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400Ωcm, which is at least one order of magnitude greater than the typical value (1–10Ωcm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported.

Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High ${\rm I}_{\rm ON}/{\rm I}_{\rm OFF}$ Ratio Ge FinFETs

Integrating germanium (Ge) thin film on silicon-on-insulator (SOI) substrate and fabricating Ge fin field-effect transistors (FinFETs) are demonstrated in this paper. Directly grown Ge film on a high-resistivity thin SOI substrate provides a good platform for fabricating advanced Ge devices. The SOI structure could effectively suppress junction leakage; therefore, high ION/IOFF ratio (~5×105, at VD=0.1 V) of the drain current is achieved. Tri-gate structure provides better short-channel control abilities for the Ge FinFETs, and the drain-induced barrier lowering and threshold voltage (VTH) shift can be maintained at the level of ~110 mV/V and ~ 0.1 V, respectively, for Ge n-channel FinFET with Lchannel=120 nm and WFin=40 nm. Multifin Ge FinFET with Lchannel=170 nm and WFin=50 nm is also illustrated. Both N- and P-FinFETs possess high ION/IOFF ratio over 104. Besides, the subthreshold swing could be reduced around 25% after forming gas annealing.

Wafer-scale Cu plating uniformity on thin Cu seed layers

The wafer scale plating uniformity with thin Cu seed layer was studied. Plating experiments were performed on 300mm diameter wafers with 4nm, 5nm and 10nm thin Cu seed layers. The plating current distribution can be very nonuniform due to the high substrate resistance. In the case of extremely thin seed layer, the corrosion of Cu due to dissolved oxygen becomes significant. It may lead to exposed barrier layer near the wafer center. A modeling methodology was developed to study the Cu plating uniformity on the wafer scale. Simulation result matches well with experimental measurement and theoretical prediction. The plating uniformity and seed layer corrosion were studied for various seed layer thicknesses using the proposed modeling approach.

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

An t 86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulators, clock generation, power management, memory controller and RF portion of a WiFi transceiver in a 32 nm high-k/metal-gate RF CMOS process with high resistivity substrate. The integrated RF transceiver for 2.4 GHz 802.11g operation achieves a receive sensitivity of -74 dBm, -8 dBm IIP3 and a transmit output power of 20.3 dBm (-25 dB EVM) at 14% TX RF efficiency.

High-<formula formulatype="inline"><tex Notation="TeX">$Q$</tex></formula> Backside Silicon-Embedded Inductor for Power Applications in <formula formulatype="inline"><tex Notation="TeX">$\mu\hbox{H}$</tex></formula> and MHz Range

In this paper, a set of backside silicon-embedded inductors (BSEIs) is fabricated and characterized for potential applications in next-generation fully integrated power electronics. The fabrication technology of the BSEI is very similar to the through-silicon-via technology and has a high potential for post-CMOS integration. Without using magnetic material, an inductance as high as 13.8 μH is achieved with an effective inductance density of 0.6 μH/mm2. For the 4.5 mm × 4.5 mm BSEIs with a high substrate resistivity, an inductance between 2 and 4 μH, a dc resistance of 0.6-1.4 Ω , and a peak quality factor ranging from 18 to 23 occurring at 2-5 MHz are experimentally demonstrated. The effects of various physical design parameters are also experimentally studied, including coil outer dimension, metal width/spacing/pitch, coil shape, and silicon resistivity. These measurement results illustrate the design flexibility of the proposed BSEI technology to allow tradeoffs of key electrical properties for meeting different requirements of various integrated power electronics.

A 0.28 THz Power-Generation and Beam-Steering Array in CMOS Based on Distributed Active Radiators

In this paper, we present a scalable transmitter architecture for power generation and beam-steering at THz frequencies using a centralized frequency reference, sub-harmonic signal distribution, and local phase control. The power generation and radiator core is based on a novel method called distributed active radiation, which enables high conversion efficiency from DC to radiated terahertz power above fmax of a technology. The design evolution of the distributed active radiator (DAR) follows from an inverse design approach, where metal surface currents at different harmonics are formulated in the silicon chip for the desired electromagnetic field profiles. Circuits and passives are then designed conjointly to synthesize and control the surface currents. The DAR consists of a self-oscillating active electromagnetic structure, comprising of two loops which sustain out-of-phase currents at the fundamental frequency and in-phase currents at the second harmonic. The fundamental signal, thus gets, spatially filtered, while the second harmonic is radiated selectively, thereby consolidating signal generation, frequency multiplication, radiation of desired harmonic and filtration of undesired harmonics simultaneously in a small silicon footprint. A two-dimensional 4×4 radiating array implemented in 45 nm SOI CMOS (without high-resistivity substrate) radiates with an EIRP of +9.4 dBm at 0.28 THz and beam-steers in 2D over 80° in both azimuth and elevation. The chip occupies 2.7 mm × 2.7 mm and dissipates 820 mW of DC power. To the best of the authors' knowledge, this is the first reported integrated beam-scanning array at THz frequencies in silicon.

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5cm), resolution of 10–15μm in both coordinates, low material budget <1%X0, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180nm process and the 130nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.

(Invited) SOI Technologies from Microelectronics to Microsystems - Meeting the More than Moore Roadmap Requirements

This last decade Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency (reaching cut-off frequencies close to 500 GHz for nMOSFETs) and for harsh environments (high temperature, radiation) commercial applications. SOI also presents high resistivity substrate capabilities, leading to substantially reduced substrate losses. More recently, SOI technology has been emerging as a major contender for heterogeneous microsystems applications. In this work, we demonstrate the advantages of SOI technology for RF CMOS integration as well as for building thin film sensors on thin dielectric membrane and three-dimensional micro-electromechanical (MEMS) sensors and actuators co-integrated with their associated SOI CMOS circuitry.

Electrical characteristics of homoepitaxial p-GaSb analyzed by the p–n junction: A correction on the Hall parameter of heteroepitaxial p-GaSb/SI–GaAs

Electrical characteristics of p-GaSb are examined by applying the junction Hall effect measurement (JHEM) to homoepitaxially grown p-GaSb/n-GaSb layers, and analysis is made on the disagreement with those of an equivalent heteroepitial p-GaSb/semi-insulating (SI) GaAs. The photoluminescence spectra reveal that a large number of intrinsic defects are induced due to the lattice mismatch in p-GaSb/SI–GaAs, and the shallow donors of [SbGa] involved in the electrical conduction was significantly reduced in p-GaSb/n-GaSb. This proves that the homoepitaxial p-GaSb is quite different from the heteroepitaxial one in the electrical and the optical characteristics, and that the JHEM approach is correct in determining the Hall parameters of the epitaxial layers whose high-resistive substrates are not available.

High-Efficiency Cellular Power Amplifiers Based on a Modified LDMOS Process on Bulk Silicon and Silicon-On-Insulator Substrates With Integrated Power Management Circuitry

An RF high-voltage CMOS technology is presented for cost-effective monolithic integration of cellular RF transmit functions. The technology integrates a modified LDMOS RF power transistor capable of nearly comparable linear and saturated RF power characteristics to GaAs solutions at cellular frequency bands. Measured results for multistage cellular power amplifier (PA) designs processed on bulk-Si and silicon-on-insulator on high-resistivity Si substrates (1 kΩ·cm ) are presented. The low-band multistage PA achieves greater than 60% power-added efficiency (PAE) with more than 35.5-dBm output power. The high-band PA achieves 45%-53% PAE across the band with greater than 33.4-dBm output power. Measured linearity performance is presented using an EDGE modulation source. A dc/dc buck converter was also integrated in the PA die as the power management circuitry. Measured results for the output power, PAE, and spurious emissions in the receive band while the dc/dc converter is biasing the PA and running at different modes are reported.

Studies of vertex tracking with SOI pixel sensors for future lepton colliders

This paper presents a study of vertex tracking with a beam hodoscope consisting of three layers of monolithic pixel sensors in SOI technology on high-resistivity substrate. We study the track extrapolation accuracy, two-track separation and vertex reconstruction accuracy in π− Cu interactions with 150 and 300GeV/c pions at the CERN SPS. Results are discussed in the context of vertex tracking at future lepton colliders.

Characterisation of a thin fully depleted SOI pixel sensor with high momentum charged particles

This paper presents the results of the characterisation of a thin fully depleted pixel sensor manufactured in SOI technology on high-resistivity substrate with high momentum charged particles. The sensor is thinned to 70μm and a thin phosphor layer contact is implanted on the back-plane. Its response is compared to that of thick sensors of same design in terms of signal and noise, detection efficiency and single point resolution based on data collected with 300GeV pions at the CERN SPS. We observe that the charge collected and the signal-to-noise ratio scale according to the estimated thickness of the sensitive volume and the efficiency and single point resolution of the thinned chip are comparable to those measured for the thick sensors.

Characterisation of a Thin Fully Depleted SOI Pixel Sensor with Soft X-ray Radiation

This paper presents the results of the characterisation of a back-illuminated pixel sensor manufactured in Silicon-on-Insulator technology on a high-resistivity substrate with soft X-rays. The sensor is thinned and a low energy phosphorus implantation is performed on the back-plane. The response to X-rays from 2.12 to 8.6keV is evaluated with fluorescence radiation at the LBNL Advanced Light Source.

Terahertz detectors based on superconducting hot electron bolometers

Low noise terahertz (THz) heterodyne detectors based on superconducting niobium nitride (NbN) hot electron bolometers (HEBs) have been studied. The HEB consists of a planar antenna and an NbN bridge connecting across the antennas inner terminals on a high-resistivity Si substrate. The double sideband noise temperatures at 4.2 K without corrections have been characterized from 0.65 to 3.1 THz. The excess quantum noise factor β of about 4 has been obtained, which agrees well with the calculated value. Allan variance of the HEB has been measured, and Allan time up to 20 s is obtained using a microwave feedback method. Also, the intermediate frequency gain bandwidth (GBW) was measured using two different methods, resulting in same GBW value of about 3.5 GHz.

Possibilities for Thick, Simple-Structure Silicon X-Ray Detectors Operated by Peltier Cooling

We have proposed two types of simple-structure silicon (Si) X-ray detectors with 1.5-mm-thick high-resistivity Si substrates, which are able to be operated at reasonably low negative bias and cooled by Peltier cooling. Since the device structures are simple and the detectors require only one high voltage, the cost of the X-ray detection system can be reduced very much. Moreover, the absorption of cadmium X-ray fluorescence (energy: 23.1 keV) in 1.5-mm-thick Si is approximately 65%, whereas in commercial silicon drift detectors (Si thickness: approximately 0.3 mm), it is approximately 19%. We have simulated the electric potential distribution within the proposed detectors and carried out fundamental experiments towards the realization of the detectors.

REBULF super junction MOSFET with N + buried layer

A reduced bulk field (REBULF) super junction metal-oxide semiconductor field-effect transistor is designed for the first time with N+ buried layer in the P-type high resistance substrate. The substrate-assisted depletion effect, resulting from charge imbalance between the N and P-type pillars when the super junction is implemented on the P-type substrate, is suppressed due to the charge compensation by the N+ buried layer. The high electric field around the drain is reduced, thanks to the REBULF effect which causes the redistribution of the electric field in the drift region; thus the breakdown voltage is improved because the substrate supports more biases. The new structure features high breakdown voltage, low specific on-resistance and charge balance in drift region.

Characterisation of a pixel sensor in SOI technology for charged particle tracking

This paper presents the results of the characterisation of a pixel sensor manufactured in OKI 0.2 micron SOI technology integrated on a high-resistivity substrate, and featuring several pixel cell layouts for charge collection optimisation. The sensor is tested with short IR laser pulses, X-rays and 200 GeV pions. We report results on charge collection, particle detection efficiency and single point resolution.

Extraction and Analysis of Substrate Parameters in On-Chip Spiral Inductor Model

Inductors on high resistivity substrate, such as quartz or high resistivity silicon(HR-Si), can get better Q factor than those on low resistivity substrate, which makes it necessary to research the substrate influence on inductors. In this paper, a lumped element model for on-chip inductor that includes skin and proximity effects, substrate electric and magnetic losses at high-frequency range is presented. The proposed model has been verified with square spiral inductors with various geometrical configurations on quartz, SOI and high-resistivity silicon substrate. It shows good agreement with the simulation and tested results. This model can be easily used in circuit simulations and optimization design.

Interplay between electrical transport properties of GeMn thin films and Ge substrates

We present evidence that electrical transport studies of epitaxial $p$-type GeMn thin films fabricated on high-resistivity Ge substrates are severely influenced by parallel conduction through the substrate, related to the large intrinsic conductivity of Ge due to its small band gap. Anomalous Hall measurements and large magnetoresistance effects are completely understood by taking a dominating substrate contribution as well as the measurement geometry into account. It is shown that substrate conduction persists also for well-conducting, degenerate, $p$-type thin films, giving rise to an effective two-layer conduction scheme. Using $n$-type Ge substrates, parallel conduction through the substrate can be reduced for the $p$-type epilayers, as a consequence of the emerging $\mathit{pn}$-interface junction. GeMn thin films fabricated on these substrates exhibit a negligible magnetoresistance effect. Our study underlines the importance of a thorough characterization and understanding of possible substrate contributions for electrical transport studies of GeMn thin films.

Integration of RF inductors and filters on mesoporous silicon isolation layers

AbstractIn this paper, we present electrochemical etching conditions to obtain thick mesoporous silicon electrical insulating layers for RF applications from high resistivity substrates (30–50 Ω cm). We present the realization and the characterization of spiral inductors on thick mesoporous silicon layers. Indeed, PSi layers reduce significantly the resistive and capacitive losses of the substrate, so, quality factor and resonant frequencies are improved for integrated inductors. In complement, we develop the integration of such devices in notch filters and we show the first measurement results on 100 µm thick mesoporous silicon layers.