High Radix Research Articles

On the topological properties of HyperX

In modern world, all sciences especially engineering have insatiable demand for more power of processing. Although the use of modern micro-architectures has increased the performance of processors, this increment is only part of speeding up in responding such these demands. In fact, the need of some applications to parallel systems in large scales makes these systems more popular. Therefore, these systems are only the possible way of performing enormous computing power for applications with high performance computing. This paper comprehensively studies the topological properties of a class of n-D networks that are called HyperX from different aspects. In this paper we are going to provide a detailed description of HyperX topology in an algebraic framework with basic features (such as regularity, symmetry, etc.). The important parameters in this topology are evaluated parametrically and compared with other topologies. Having expressed this fact, we emphasize that our study is among the very few attempts reported in the literature to analyze the important parameters that can capture the performance behavior of HyperX topology. Since HyperX has many advantages of high radix switch components, it becomes a serious competitor against the other topologies and high radix networks. Hence, this study leads to finding an optimum topology for these kinds of networks.

Logical Design of Quaternary Signed Digit Conversion Circuit and its Effectuation using Operational Amplifier

In binary number system carry is a major problem in arithmetical operation. We have to suffer O(n) carry propagation delay in n-bit binary operation. To overcome this problem signed digit is required for carry free arithmetical operation. Further, literature reviews suggest that multi-valued logic (MVL) would be a better choice to address the problem of developing faster chips for performing faster computational operation. Quaternary Signed Digit (QSD) have a major contribution in higher radix (=4) carry free arithmetical operation. For digital implementation, the signed digit quaternary numbers are represented using 3-bit 2's compliment notation. In this paper, a simple and new technique of binary (2's compliment) to QSD conversion is proposed and described. Well-known operational amplifier (OPAMP) based digital to analog converter circuit is also given to verify the above technique.

Implementation of very high radix division in FPGAs

A new approach in multiplication-based dividers for FPGAs is proposed. It relies on very high radix algorithms with prescaling of divisor and dividend. The required multiplications (prescale factor computations, divisor prescaling, dividend prescaling, and the division main iteration) are performed using a simplified version of a multiply–add fused unit, which integrates well into the FPGA specific structure. It is shown that the proposed implementation uses a small number of DSP blocks (three for IEEE simple precision, five for IEEE double precision and eight for IEEE quad precision for Spartan 6 devices), in order to perform the division.

The role of optics in future high radix switch design

For large-scale networks, high-radix switches reduce hop and switch count, which decreases latency and power. The ITRS projections for signal-pin count and per-pin bandwidth are nearly flat over the next decade, so increased radix in electronic switches will come at the cost of less per-port bandwidth. Silicon nanophotonic technology provides a long-term solution to this problem. We first compare the use of photonic I/O against an all-electrical, Cray YARC inspired baseline. We compare the power and performance of switches of radix 64, 100, and 144 in the 45, 32, and 22 nm technology steps. In addition with the greater off-chip bandwidth enabled by photonics, the high power of electrical components inside the switch becomes a problem beyond radix 64. We propose an optical switch architecture that exploits highspeed optical interconnects to build a flat crossbar with multiplewriter, single-reader links. Unlike YARC, which uses small buffers at various stages, the proposed design buffers only at input and output ports. This simplifies the design and enables large buffers, capable of handling ethernet-size packets. To mitigate head-of-line blocking and maximize switch throughput, we use an arbitration scheme that allows each port to make eight requests and use two grants. The bandwidth of the optical crossbar is also doubled to to provide a 2x internal speedup. Since optical interconnects have high static power, we show that it is critical to balance the use of optical and electrical components to get the best energy efficiency. Overall, the adoption of photonic I/O allows 100,000 port networks to be constructed with less than one third the power of equivalent all-electronic networks. A further 50% reduction in power can be achieved by using photonics within the switch components. Our best optical design performs similarly to YARC for small packets while consuming less than half the power, and handles 80% more load for large message traffic.

A Low-power and High-performance Radix-4 Multiplier Design Using a Modified Pass-transistor Logic Technique

This paper describes a 1-bit adder designed using the modified complementary pass transistor logic technique. The proposed adder was implemented in an 8 × 8 bit high radix multiplier circuit. This paper describes the proposed adder technique for obtaining high speed, lower area, less power dissipation and lower propagation delay. The multiplier circuits were schematized using the DSCH2 schematic design tool, and their layouts were generated with the Microwind 2 VLSI layout CAD tool. The parameter analyses were performed with a BSIM4 analyzer. Two unsigned multipliers were designed using the proposed modified complementary pass-transistor logic (CPL) adder cell, namely a Carry Save Array multiplier (CSA multiplier) and a Baugh-Wooley multiplier, for comparison with our proposed adder cell-based high radix multiplier. The proposed adder cell-based CSA multiplier and Baugh-Wooley multiplier, as well as other existing multipliers, were compared with the high radix multiplier circuit in terms of power dissipation, propagation delay, latency, throughput, Energy Per Instruction and area. Our proposed 1-bit adder and adder-based high radix multipliers demonstrated better performance than other published results.

Rhinoplasty in the Hispanic Patient

In the United States, rhinoplasty has traditionally been performed in Caucasian patients. Ethnic rhinoplasty is often thought of as a procedure done to reshape the nose of a black or Asian patient. Little attention has been paid to rhinoplasty in Hispanic patients. There has been a large increase in the Hispanic population of the United States, and plastic surgeons will see a concomitant rise in requests for rhinoplasty among this population. In an effort to increase our understanding of Hispanic rhinoplasty, a retrospective review of a senior surgeon's experience was performed. A retrospective chart review was done examining the senior author's (S.S.) rhinoplasty practice over the past 10 years. Hispanic patients presenting for aesthetic and corrective rhinoplasty (cleft patients were excluded) were analyzed. The Hispanic nose was divided into three archetypes. Type I is characterized by a high radix and prominent vault; these noses should be corrected by dorsal reduction and resection of caudal septum. Type II is characterized by a dependent tip with inadequate projection; dorsal augmentation with diced cartilage and tip support with cartilage grafts are important. Osteotomies should generally be avoided in this group. Type III noses are characterized by a broad nasal base with thick skin and a wide tip; rhinoplasty in this group requires correction of the dorsum-base disproportion using several techniques including columellar struts, tip grafts, and dorsal augmentation. Hispanics are projected to become the largest minority population within the next 10 years, and rhinoplasty in this population will become more frequent over time. It behooves plastic surgeons to become familiar with the different archetypes of Hispanic noses and appropriate corrective techniques for each.

An efficient fixed-point IMDCT algorithm for high-resolution audio appliances

In this paper, we propose an efficient fixed-point IMDCT algorithm for high-resolution audio (or audio/video) appliances such as digital media receiver (DMR) and high-end portable media player (PMP). A novel block floating-point algorithm and a method of reducing the number of guard bits are proposed to implement IMDCT. The former can compute IFFT-based IMDCT with same efficiency as higher radix IFFT and has same number of guard bits as radix-2 IFFT. The latter can reduce the number of guard bits based statistical bit growth pattern. Experimental results using high-resolution advanced audio coding (AAC) decoder show that the 32-bit IMDCT implemented by the proposed algorithm can comply with a 24-bit AAC decoder with 20% ~ 50% less computational complexity when compared with existing 48-bit IMDCT. The proposed algorithm can be used efficiently for low-complexity implementation of high-resolution audio appliances.

Fractional Subblocking for Partial Transmit Sequence OFDM

Partial transmit sequence (PTS) is a well known technique used to reduce the peak-to-average power ratio (PAPR) of an orthogonal frequency division multiplexing (OFDM) signal. However, it has relatively high complexity due to the computation of multiple inverse fast Fourier transforms (IFFTs). To reduce this complexity, we use intermediate signals within a decimation in frequency (DIF) radix IFFT and propose a new PTS subblocking technique which requires the computation of only partial IFFTs. Performance results are presented which show a PAPR reduction similar to that with other techniques such as original PTS (O-PTS). Further, we show that complexity reduction can be achieved with either low or high radix IFFT algorithms.

Beyond Fat--tree: Unidirectional Load--Balanced Multistage Interconnection Network

The fat-tree is one of the most widely-used topologies by interconnection network manufacturers. Recently, it has been demonstrated that a deterministic routing algorithm that optimally balances the network traffic can not only achieve almost the same performance than an adaptive routing algorithm but also outperforms it. On the other hand, fat-trees require a high number of switches with a non-negligible wiring complexity. In this paper, we propose replacing the fat--tree by a unidirectional multistage interconnection network (UMIN) that uses a traffic balancing deterministic routing algorithm. As a consequence, switch hardware is almost reduced to the half, decreasing, in this way, the power consumption, the arbitration complexity, the switch size itself, and the network cost. Preliminary evaluation results show that the UMIN with the load balancing scheme obtains lower latency than fat--tree for low and medium traffic loads. Furthermore, in networks with a high number of stages or with high radix switches, it obtains the same, or even higher, throughput than fat-tree.

Higher Radix and Redundancy Factor for Floating Point SRT Division

The execution performances of the Sweeney, Robertson, Tocher (SRT) division algorithm depend on two parameters: the radix-r and the redundancy factor p. In this paper, a study of the effect of these parameters on the division performances is presented. At each iteration, the SRT algorithm performs a multiplication by the quotient digit qi+1. This last can be just a simple shift, if the digit qi i +1is a power of two (qi+1 = 2k), otherwise, the SRT iteration needs a multiplier. We propose, in this work, an approach to circumvent this multiplication by decomposing the quotient digit qi+1 into two or three terms multiples of 2. Then, the multiplication is carried out by simple shifts and a carry save addition. The implementation of this approach on Virtex-II field-programmable gate-array (FPGA) circuits gives best performances than the approach which uses the embedded multipliers 18times18 bits. The iterations delays are operands sizes independent. The reduction tree delays are at most equivalent to the delay of two Virtex-II slices. This approach was tested for the 4, 8, and 16 radixes in the two cases of minimum and maximum redundancy factors. By this study, we conclude that the use of the radix-8 with a maximum redundancy factor gives the best performances by using our approach for the double precision computation of the SRT division.

A low complexity selective mapping OFDM using multiple IFFT stages

A low complexity Selective Mapping (SLM) technique for reducing the Peak-to-Average Power Ratio (PAPR) of an Orthogonal Frequency Division Multiplexing (OFDM) signal is introduced. The intermediate signals within an N-point IFFT using a radix Decimation In Time (DIT) or Decimation In Frequency (DIF) IFFT algorithm are used to generate the phase sequences. It is shown that DIF provides lower multiplicative complexity in generating the SLM sequences compared to DIT, with the same PAPR reduction. In addition, a high radix FFT algorithm provides better PAPR reduction performance per stage with less multiplicative complexity compared to a low radix algorithm. We further reduce the computational complexity by proposing a low computational complexity technique based on multiplying the phase sequences at multiple IFFT stages. This new technique greatly reduces the multiplicative complexity while providing similar PAPR reduction to Ordinary SLM (O-SLM). The additive complexity is also reduced.

High-performance two's complement divider

This paper presents a novel area-efficient two's complement high radix divider without affecting the high speed of the radix- 2 k structure. In the proposed approach, only the odd values (rather than all the 2 k values) of the quotient digit set are used to generate the multiples of divisor. Moreover, the set of ( N + k + 1 ) -bit additions are replaced with a set of few most significant bits ( k + 2 bits) additions followed by two ( N + 3 ) -bit additions only. The new radix- 2 k structure has been evaluated for different values of k. It is shown that the silicon area required by the new design could be as low as 15% of that of the conventional two's complement radix- 2 k architecture for radix-64 (20% for radix-32) while the speed is nearly the same. Despite that the proposed algorithm is originally developed in order to improve the performance of the two's complement approach, it has also been compared with the redundant SRT algorithm. The area–time ratios of the new radix-16 and radix-32 dividers to that of the SRT divider are equal to 85% and 77%, respectively.

Scaling and Better Approximating Quantum Fourier Transform by Higher Radices

Quantum Fourier transform (QFT) plays a principal role in the development of efficient quantum algorithms. Since the number of quantum bits that can be built is limited, while many quantum technologies are inherently three (or more) valued, we consider extending the reach of the realistic quantum systems by building a QFT over ternary quantum digits. Compared to traditional binary QFT, the q-valued transform improves approximation properties and increases the state space by a factor of (q/2)n. Further, we use nonbinary QFT derivation to generalize and improve the approximation bounds for QFT

Scalable hardware implementing high-radix Montgomery multiplication algorithm

This paper presents a new scalable hardware implementing modular multiplication. A high radix Montgomery multiplication algorithm without final subtraction is used to perform this operation. An alternative proof for the final Montgomery multiplication by 1, removing the condition on the modulus, is given. This hardware fits in any chip area and is able to work with any size of modulus. Unlike other scalable designs only one cell is used. This cell contains standard and well optimized digit multiplier and adder. Time-area trade-offs are also available before hardware synthesis for differents sizes of internal data path. The pipeline architecture of the multiplier component increases the clock frequency and the throughput. Time-area trade-offs are analyzed in order to make the best choice for given time and area constraints. This architecture seems to provide a better time-area compromise than previous scalable hardware.

Improvement to Montgomery Modular Inverse Algorithm

After a comprehensive study on the Montgomery modular inverse algorithm and its revised versions, two modified high radix algorithms are proposed which utilize higher radix to reduce iterations needed without increasing complexity much, thereby accelerating the process. The radix-4 algorithm can reduce the average number of iterations from 1.4 n to 0.82 n and a software experiment shows the speedup is about 11 percent and iterations are 41.5 percent less on average. The radix-8 algorithm can reduce the average number of iterations to 0.73 n, but it is more complicated, which makes it suitable only for very large numbers (2,048 bits) in the experiment, where the speedup can be 13-18 percent. The proposed algorithms are suitable for software implementations on general-purpose microprocessors

Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits

A novel algorithm for full-addition of two signed, higher-radix numbers is proposed and implemented by combining multi-valued logic min, max, literal and cyclic operators. Owing to disjoint terms involved, multi-valued logic min and max operators are replaced with ordinary transmission operation and sum, respectively. A multi-valued logic cyclic gate is designed by using a current-mode threshold circuit while the literal is realised by only voltage-mode switching circuits. The threshold circuit employed within the cyclic gate exhibits improved dynamic behaviour compared to its previous counterparts employing voltage-mode binary logic switching circuits. It also allows much higher radices compared to previous current-mode threshold circuits owing to its superior mismatch properties. Thus, the cyclic gate achieves a superior performance compared to its predecessors. As a direct extension to cyclic operation in radix-8, a resultant single-digit, radix-8 full-adder and its 3-bit counterpart voltage-mode circuits are designed and their performance compared. It is shown that the developed signed addition algorithm can be realised by using the proposed full-adder. Finally, the algorithm is also exploited for a multi-digit case. Simulation results demonstrate that proposed architectures can be used in high-performance arithmetic units.

On MultiModuli residue number systems with moduli of forms r/sup a/, r/sup b/-1, r/sup c/+1

The residue number system (RNS) is an integer system appropriate for implementing fast digital signal processors since it can support parallel, carry-free, high-speed arithmetic. One of the most important considerations when designing RNS systems is the choice of the moduli set. This is due to the fact that the system's speed, its dynamic range, as well as its hardware complexity depend on both the forms and the number of the chosen moduli. When performing high radix-r(r>2) arithmetic, moduli of forms r/sup a/, r/sup b/-1 and r/sup c/+1 imply simple RNS arithmetic and efficient weighted (radix-r)-to-RNS and RNS-to-weighted (radix-r) conversions. In this paper, new multimoduli high radix-r RNS systems based on moduli of forms r/sup a/, r/sup b/-1 and r/sup c/+1 are presented. These systems will be derived from some recently developed theory. Such systems including moduli of forms r/sup a/, r/sup b/-1 and r/sup c/+1 are appropriate for multiple-valued logic implementations or high radix (r>2) arithmetic using binary logic. The new RNS systems are balanced, achieve fast and simple RNS computations and conversions and implement large dynamic ranges. The specific case of the binary (radix r=2) domain is also presented.

Microarchitecture of a High-Radix Router

Evolving semiconductor and circuit technology has greatly increased the pin bandwidth available to a router chip. In the early 90s, routers were limited to 10Gb/s of pin bandwidth. Today 1Tb/s is feasible, and we expect 20Tb/s of I/O bandwidth by 2010. A high-radix router that provides many narrow ports is more effective in converting pin bandwidth to reduced latency and reduced cost than the alternative of building a router with a few wide ports. However, increasing the radix (or degree) of a router raises several challenges as internal switches and allocators scale as the square of the radix. This paper addresses these challenges by proposing and evaluating alternative microarchitectures for high radix routers. We show that the use of a hierarchical switch organization with per-virtual-channel buffers in each subswitch enables an area savings of 40% compared to a fully buffered crossbar and a throughput increase of 20-60% compared to a conventional crossbar implementation.

Area-efficient nonrestoring radix- division

This paper presents an area-efficient twos complement high radix division algorithm and its architecture. The advantage of using high radix division is to generate more quotient bits per iteration while binary division results in one bit per iteration. In the conventional restoring radix-2^k division, the selection of the quotient digit requires the use of all the multiples of the divisor. As a result, the area increases exponentially (area of radix 2^k divider is about 2^k times the area of binary divider) while the speed increases linearly (speed of radix 2^k divider is approximately k times that of binary divider). In this paper, a new algorithm that makes use only of the even multiples of the divisor is proposed. The area is nearly halved since the number of multiples is reduced from 2^k to 2^k^-^1. We use the even multiples rather than the odd ones because the even multiples are easier to generate and some of them are produced by simply shifting the divisor. For example, the even multiples 2D and 4D are generated by shifting D one and two bits to the left, respectively, while the odd multiples 3D and 5D require an addition of D to 2D and D to 4D, respectively.

Secondary radix recodings for higher radix multipliers

For progressively higher radices, the reduction in partial products obtained by the well-known modified Booth multiplier recoding is offset by the need to precompute a rapidly increasing store of odd multiples of the multiplicand as inputs to each partial product generator (PPG). We propose secondary radix multiplier recoding schemes reducing the number of odd multiples required in the store for very high radix recodings (e.g., radix 2/sup r/ for 5 /spl les/ r /spl les/ 16). The proposed recoding schemes allow reduction of the number of partial products in the implementation by factors between and beyond the reduction factors of 2, 3, and 4 that can be achieved by traditional Booth recodings to radices 4, 8, and 16, respectively. We develop the theory of these recodings and provide methodology for secondary radix selection. Finally, we summarize latency and cost evaluations of selected implementations indicating potential cost and performance/cost advantages for practical operand sizes.