Abstract
A new approach in multiplication-based dividers for FPGAs is proposed. It relies on very high radix algorithms with prescaling of divisor and dividend. The required multiplications (prescale factor computations, divisor prescaling, dividend prescaling, and the division main iteration) are performed using a simplified version of a multiply–add fused unit, which integrates well into the FPGA specific structure. It is shown that the proposed implementation uses a small number of DSP blocks (three for IEEE simple precision, five for IEEE double precision and eight for IEEE quad precision for Spartan 6 devices), in order to perform the division.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
