High-power Transistors Research Articles

1 W/mm Output Power Density for H-Terminated Diamond MOSFETs With Al2O3/SiO2Bi-Layer Passivation at 2 GHz

We have demonstrated a novel method of depositing ALD-Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /PECVD-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> bi-layer dielectric to passive the surface channels of the hydrogen-terminated diamond (H-diamond). After Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> passivation, the surface current increased with time and then tended to be saturated. Afterwards, it became much more stable and showed a larger current than an unpassivated counterpart. The H-diamond MOSFETs were fabricated by using this bi-layer passivation structure and an extremely low Ohmic contact resistance of 0.87 Ω·mm was obtained. The H-diamond RF MOSFET with gate length of 0.45 μm achieved a high current density of -549 mA/mm and an extrinsic fT/fmax of 15/36 GHz. By load-pull measurement, a high output power density of 1.04 W/mm was obtained at frequency of 2 GHz. The results reveal that it is a promising solution for high-stable and high-power diamond transistors by using the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> bi-layer passivation.

High electron mobility of AlxGa1−xN evaluated by unfolding the DFT band structure

We calculate the alloy-disorder-limited electron mobility of AlxGa1−xN from first principles. AlxGa1−xN is a technologically important ultra-wide-bandgap alloy with promise in light emitting diodes and high-power transistors. Alloying introduces statistical disorder, which causes electrons to scatter between different crystal-momentum states, leading to a reduction in mobility for intermediate alloy compositions. The corresponding lifetime, which appears as an energy broadening in the band structure, can be evaluated by unfolding the band structure from the supercell basis to the primitive-cell basis. We fit the first-principles band broadening with a model scattering potential and evaluate the low-field electron mobility using the semiclassical Boltzmann transport equation in the relaxation-time approximation. Our calculated mobility is in agreement with experimental values. We also find the lowest alloy-scattering electron mobility (total electron mobility) across the entire composition range to be 186 cm2/V s (136 cm2/V s), which is comparable to the highest electron mobility predicted in the competitor system, β-(AlxGa1−x)2O3. Our results elucidate the intrinsic limits imposed by alloy disorder on electron transport in AlxGa1−xN.

Improved measurement techniques for high-power transistor modeling.

Measurement for modeling of the high-power transistors is difficult due to its high-power and low-impedance characteristics. In this paper, novel methods and devices were designed and applied to achieve precise measurements of the high-power transistors. Fixtures capable of withstanding high voltage and current were designed to replace traditional radio frequency (RF) probes for higher power capacity. To reduce the impact of capacitive and inductive components of traditional bias tees on the rising/falling edge, two wideband 90° hybrid couplers that were connected back-to-back were designed for pulsed measurements. The measurement system of stable S-parameters with the Vector Network Analyzer (VNA) was reported, which could protect the devices and laboratory equipment from damage of self-oscillation. Application of several innovative approaches enabled accurate I-V characteristic and S-parameters measurements of high-power transistors in DC or pulsed mode. Experimental results of a 30 W gallium nitride high-electron-mobility transistor verified the validity.

A Bipolar Transistor-Based High-Power Chaotic Oscillator with Selected Inertia

The feasibility of creating a high-power wideband source of chaotic microwave signals that is constructed around a single high-power bipolar transistor has been demonstrated for the first time. This has become possible after implementing a selected-inertia oscillator. Theoretical calculations supporting the idea of fabricating such an oscillator are presented. A hybrid integrated prototype of a selected-inertia chaotic oscillator that is based on a 2T982A-2 high-power transistor has been designed. The feasibility of generating chaotic microwave signals with a center frequency of 4.55 GHz and an overall power of 1.1 W has been proved. The effective width of the chaotic signal power spectrum equals 11% at a spectral characteristic ripple of 3 dB, the spectral density of noise oscillations is 2.2 × 10–3 W/MHz, and the e1fficiency is 15%.

(Invited) Technology of Gallium Nitride Crystal Growth - Challenges and Perspectives

It is well known that gallium nitride (GaN) is the basic material for fabricating optoelectronic devices as Light Emitting Diodes (LEDs) and Laser Diodes (LDs). GaN is also an attractive choice for electronic high-frequency and high-power devices. This is due to its wide band gap, high electron velocity, high breakdown field strength and high thermal conductivity. Most of the mentioned GaN-based devices are built on foreign substrates (sapphire, silicon, or silicon carbide). For many years, there was no mass production of native substrates. This happened because GaN crystal growth is quite a challenging process. The compound melts congruently at high temperature and extremely high nitrogen pressure (>6 GPa). Thus, today, it is impossible to grow GaN from the melt. The crystals should be obtained by other techniques requiring lower pressure and temperature. Crystallization from gas phase, solution, or any combination thereof must be included. For more than three decades, crystallization of bulk GaN has remained a big challenge for the nitride community. Work on developing bulk GaN has mainly been motivated by the LD market. All commercially available LD epi-structures are built on GaN wafers. Today, however, not only the LDs, but also the electronic industry and the demand for vertical high power transistors and diodes seem to be the driving force for crystallizing bulk GaN. Thus, GaN substrates of relatively high quality have recently become available. Today, GaN is crystallized by three main methods: i/ sodium flux (Na-flux); ii/ halide vapor phase epitaxy (HVPE); and iii/ basic or acidic ammonothermal growth. Perspectives of all the mentioned above technologies will be presented in this lecture. Special attention will be paid to the basic ammonothermal method and HVPE. It will be shown that growth from the vapor phase needs a new philosophy. The crystallization processes on foreign seeds (sapphire and gallium arsenide) reached their maximum possibilities. Despite many tricks during crystal growth runs the structural quality as well as yield of the obtained GaN crystals and wafers are very low and cannot be improved. The only way is GaN-on-GaN crystallization. Recently, significant progress has been presented in the basic ammonothermal method. High structural quality crystals of lateral size larger than 2 inches and thickness exceeding 6 mm were obtained in one crystal growth process. Use of ammonothermally grown GaN as seed for HVPE will be presented. All challenges and difficulties to grow bulk GaN from the vapor phase will be demonstrated. Scenarios for the further development of bulk GaN crystallization will be shown. Important parameters of GaN substrates for epitaxy of optoelectronic and electronic device structures will be discussed. A new way of better controlling the electrical properties of GaN crystals and wafers will be proposed.

Research on VRM in RF PA System Based on Enhancement Mode GaN HEMT

As a key part of the RF PA system, VRM (Voltage-Regulate-Modulator), whose main role is to offer pulse voltage for RF power transistor, is often slighted. As a result, VRM has been a restraining factor now. In order to realize the needs of high speed and high frequency, a new method based on enhancement mode GaN HEMT of designing VRM is proposed in this paper. By using this method, the rise time and fall time of VRM could be as about 10ns with the peak voltage 75V and the peak current 150A, which is quite suitable for driving high voltage and high power GaN-based RF power transistor.

Band Alignment of ScxAl1–xN/GaN Heterojunctions

ScAlN is an emergent ultrawide-band-gap material with both a high piezoresponse and demonstrated ferroelectric polarization switching. Recent demonstration of epitaxial growth of ScAlN on GaN has unlocked prospects for new high-power transistors and nonvolatile memory technologies fabricated from these materials. An understanding of the band alignments between ScAlN and GaN is crucial in order to control the electronic and optical properties of engineered devices. To date, there have been no experimental studies of the band offsets between ScAlN and GaN. This work presents optical characterization of the band gap of molecular beam epitaxy grown ScxAl1-xN using spectroscopic ellipsometry and measurements of the band offsets of ScxAl1-xN with GaN using X-ray photoemission spectroscopy, along with a comparison to first-principles calculations. The band gap is shown to continuously decrease as a function of increasing ScN alloy fraction with a negative bowing parameter. Furthermore, a crossover from straddling (type-I) to staggered (type-II) band offsets is demonstrated as Sc composition increases beyond approximately x = 0.11. These results show that the ScAlN/GaN valence band alignment can be tuned by changing the Sc alloy fraction, which can help guide the design of heterostructures in future ScAlN/GaN-based devices.

Individual forecasting of reliability of bipolar transistors by using electrical voltage as a simulation factor

Individual forecasting of the reliability of semiconductor devices, taking into account gradual failures, is an urgent task, as it allows you to choose highly reliable instances for critical electronic devices of long-term functioning. In relation to bipolar transistors, an approach is proposed that allows us to solve this problem by using the voltage applied to the collector-emitter junction as a simulated effect. Using the example of highpower bipolar transistors of the KT872A type, it is shown how the problem is solved. For the sample of transistors of this type using the results of a training experiment, two equations were obtained to describe the electrical parameter under consideration (a static base current transfer coefficient in a circuit with a common emitter), the value of which judges the absence or presence of a gradual failure for a specific instance. The first equation shows how the electrical parameter changes on average depending on the voltage applied to the collector – emitter junction. The second equation describes the average degradation of the electrical parameter during long-term operating time of transistors. Based on these two equations, a simulation model of the reliability of bipolar transistors of the type in question is obtained in the form of a communication function that shows what level of simulation voltage corresponds to a given operating time. As applied to the transistors of the type under consideration, the obtained simulation model allows us to individually predict reliability by the gradual failures of the same type of samples that did not participate in the training experiment. To do this, first determine the value of the simulation voltage corresponding to a given operating time. This is achieved by substituting a given operating time into the model. The individual forecasting of the reliability of a new onetype instance consists in measuring the electrical parameter of this instance at a voltage on the transistor collector corresponding to the calculated simulation value, and comparing the measurement result with the norm set on the electrical parameter.

Novel Low-Side/High-Side Gate Drive and Supply With Minimum Footprint, High Power Density, and Low Cost for Silicon and Wide-Bandgap Transistors

High-power silicon field-effect transistors as well as insulated gate bipolar transistors and particularly wide-bandgap semiconductor transistors typically need negative turn-off voltage for a secure off-state, resilience to spurious turn on, and rapid transition through the saturation mode. We present a gate driver configuration with compact and very efficient supply of the high and low sides of power transistor bridges with asymmetric bipolar control voltages without the need for costly and lossy isolated dc-dc converter and only low-voltage active components. The underlying negative voltage gate driver supply circuit consists of only a few cost-efficient components, its electrical potential is referenced to the source of the controlled semiconductor power switch, and its operation is synchronized with the gate driver output. It outcompetes the established use of isolated dc-dc converters in gate circuits with negative voltage needs with respect to cost, size, reliability, and efficiency. Importantly, the proposed negative voltage supply allows bootstrapping without the need for controllable high-voltage semiconductors for the sake of further cost reduction. We present detailed design rules of the circuit and experimentally validate circuit and control. In the automotive prototype implementation, size of the gate driver supply was reduced by 61%, cost by 57%, and loss by more than 16%.

A Self-Regulating Gate Driver for High-Power IGBTs

To gain accurate control of the whole switching transients, this article proposes a self-regulating voltage-source gate drive (SRVSD) method for high-power insulated gate bipolar transistors (IGBTs) working under hard switching conditions. The SRVSD has a high-speed circuit capable of adjusting drive levels. With high-speed feedbacks, the on-board field programmable gate array (FPGA) identifies each switching stage and accordingly varies drive voltages. In this way, switching delay, diC/dt and dvCE/dt are regulated individually. The SRVSD allows accelerated delays and dvCE/dt stages without increasing diC/dt. Based on their principles, SRVSD is compared with existing active drivers comprehensively to verify its delay and loss reductions performance. By experiments, compared to conventional gate drive (CGD), SRVSD achieves at most 80%, 72% reductions in turn-on and turn-off delays, and 58%, 31% reductions in turn-on and turn-off losses at identical current/voltage overshoots. Moreover, the proposed adaptive control concept is verified in this article. Within several cycles, this concept automatically regulates durations of all delay, diC/dt and dvCE/dt stages to reach individual target values, largely independent of switching conditions. A practical piecewise linear switching-based loss model is proposed. Combined with SRVSD, this practical loss model can offer convenient sensing and control of switching losses in an accurate and online manner.

Investigation of the Effect of Atomic Composition on the Plasma-Chemical Etching Rate of Silicon Nitride in High-Power Transistors Based on an AlGaN/GaN Heterojunction

The effect of atomic composition on the rate of the plasma-chemical etching of silicon nitride in high-power transistors based on an AlGaN/GaN heterojunction is studied. It is shown how the subsequent process of its plasma-chemical etching depends on the configuration of the incorporation of hydrogen impurity atoms into the molecular structure of silicon nitride deposited in the plasma. The dependence of the etching rate on the process parameters (the working pressure in the chamber, the plasma-generator power, the working-gas flows, and the deposition temperature) is investigated. It is shown that the etching rate of the HxSirNzHy film is independent directly on the hydrogen content but significantly depends on the ratio of [Si–H]/[N–H] bonds. The etching rate of HxSirNzHy in high-density plasma at low powers is much less dependent on the configuration of hydrogen bonds than the etching rate of this dielectric in a buffer etchant.

A New Modeling Technique for Microwave Multicell Transistors Based on EM Simulations

Dealing with high-power operation (i.e., >100 W) is extremely critical to power-amplifier designers due to the lack of accurate transistor models of multicell (i.e., powerbar) devices. The reason is twofold: from one side, it is extremely difficult to characterize high-power transistors (e.g., device instability, thermal issues, microwave instrumentation costs, and measurement uncertainty that drastically increases with the investigated power level); and from the other side, the scaling proprieties of the model, moving from the unit-cell device to the multicell one, are inherently poor due to the different passive access structures to the active-device area. In this article, for the first time, an accurate modeling technique oriented to multicell devices is described, which allows one to extract a compact model of a multicell transistor showing similar prediction accuracy of the unit-cell one. Our assumptions have been widely demonstrated in the manuscript by a comprehensive characterization campaign from small- to large-signal operations carried out on both the unit- and multicell devices.

Limitations and Guidelines for Damage Estimation Based on Lifetime Models for High-Power IGBTs in Realistic Application Conditions

Statistical lifetime models for high-power insulated-gate bipolar transistors (IGBTs) are developed based on results from power-cycling experiments and relate lifetime expectancy to the well-defined conditions of a laboratory experiment. In most cases, predefined cyclic-stress conditions are repeatedly applied until the power device under test reaches its end of life. However, in real applications, power modules are exposed to nonrepetitive stress patterns that can be very different from the power-cycling conditions. A well-established lifetime estimation method suggests decomposing the stress pattern into individual components, whose damage can be calculated using a lifetime model. These damage contributions are then summed up in order to estimate the consumed or the remaining lifetime of a device. When comparing the estimation results to field measurements though, they often fail to match the real behavior of a power device. This article points out the uncertainties that appear in this process of applying a lifetime model on stress patterns deriving from field applications. The main purpose is to present typical sources of errors and discuss how severely these may impact the lifetime estimation.

Methods for the Separation of Failure Modes in Power-Cycling Tests of High-Power Transistor Modules Using Accurate Voltage Monitoring

The accurate measurement of on-state device voltage during power-cycling tests can deliver important information about the health of the tested power electronics components. In this article, we present the major aspects of how a power-cycling test can be set up to enable high-resolution device voltage monitoring, during both heating and cooling stages, and discuss the effect of some important parameters on the arising failure modes. The thermal transient of the component can also be captured in these setups. We show how the structure functions calculated from the captured thermal transients can be used to reveal the location of degradation in the module structure. Finally, the method for identification of bond-wire cracking and lift-off using only the measured voltage curves, is shown.

Growth and physical characterization of high resistivity Fe: β-Ga2O3 crystals**Project supported by the Scientific and Innovative Action Plan of Shanghai, China (Grant No. 18511110502) and Equipment Pre-research Fund Key Project, China (Grant No. 6140922010601).

High quality 0.02 mol%, 0.05 mol%, and 0.08 mol% Fe: β-Ga2O3 single crystals were grown by the floating zone method. The crystal structure, optical, electrical, and thermal properties were measured and discussed. Fe: β-Ga2O3 single crystals showed transmittance of higher than 80% in the near infrared region. With the increase of the Fe doping concentration, the optical bandgaps reduced and room temperature resistivity increased. The resistivity of 0.08 mol% Fe: β-Ga2O3 crystal reached to 3.63 × 1011 Ω ⋅cm. The high resistivity Fe: β-Ga2O3 single crystals could be applied as the substrate for the high-power field effect transistors (FETs).

THERMOELECTRIC SEMICONDUCTOR DEVICES FOR THERMAL STABILISATION OF REA POWERFUL TRANSISTORS

Abstract. Aim. The aim of the study is to analyse the problem of heat dissipation in high-power transistors and develop devices for their thermal stabilisation when used in electronic equipment. Method. A method is proposed for testing power transistors using a device to to ensure thermal stabilisation in the stating volume by means of a two-position temperature controller along with a model for the use of these components in electronic devices. The proposed devices support high thermal stabilisation accuracy of power transistors in a radioelectronic device system allowing temperature to be maintained at a given level with high accuracy by means of a thermoelectric battery. Results. Device designs were developed for increasing the accuracy of thermal stabilisation of power transistors with high efficiency, low energy consumption and small size. Conclusion. Based on the results of experimental studies, optimal designs for devices for the thermostabilisation of radioelectronic device components that dissipate significant power during their operation are presented. The devices can be used to increase the accuracy of thermal stabilisation of the radioelectronic device element by means of a working substance whose melting point coincides with its thermal stabilisation temperature. The developed devices have the following functions: the thermoelectric battery sections of the thermoelectric battery will be sequentially disconnected depending on the electrical signals from the temperature sensors to which the solid phase of the working substance has moved. The battery of the thermoelectric module (TEM) removes excess heat from the heat-stabilising substance while maintaining the required temperature of the radioelectronic device element. Excess heat from the heat-generating junctions of the TEM battery is removed by the heat exchanger. During melting of the working substance, the temperature of the thin-walled metal container – and, accordingly, the temperature of the CEA element – can be maintained at a constant value equal to the melting temperature of the working substance.

An improved behavioral model for high-voltage and high-power IGBT chips

High-voltage and high-power IGBT chips have a noticeable carrier storage effect, which is related to the load current. However, the research of the carrier storage effect of existing IGBT behavior models is insufficient. In this paper, An improved behavioral model for high-voltage and high-power insulated gate bipolar transistor (IGBT) chips is proposed, which could be used under different load conditions. The problems for applying the traditional behavioral model to more load conditions are discussed. The carrier behavior in the wide base region is analyzed, and the analytical expression of the carrier-storage-effect equivalent capacitance and the initial value of the tail current are given to establish the improved IGBT behavioral model. The corresponding parameter extraction method is proposed. In order to verify the improved behavioral model, an experimental platform is built for resistive load and inductive load, and the results show that the accuracy of the improved behavioral model is much better than that of the traditional model. Besides, the errors of the improved model are within 12.5% under different current and load types. Considering that the maximum error of other models that could be applied in a variety of load conditions is more than 25%, the accuracy of the model proposed in this paper is excellent.

HIGH POWER CHAOTIC OSCILLATOR

The article presents a novel design of a microwave chaotic oscillator. The oscillator contains an inertial converter for the nonlinear amplifier output signal that modulates the supply voltage of the transistor. When the inertia of the converter becomes less than 0.06, the oscillator demonstrates chaotic behavior. We present an experimental model of a chaotic oscillator based on a high power transistor 2T982A-2. The inertial converter circuit contains a diode that perform half-wave conversion of a part of the output signal and a RC circuit with a time constant equal to 0.05 of the duration of an oscillation at the central frequency of the oscillator. The output signal of the inertial converter has been applied to the emitter power supply circuit of the transistor. Modulation of the supply voltage caused the output signal of the oscillator to become a sequence of non-repeating oscillation trains with a random duration and initial phase. The frequency band of the generated chaos with an uneven power spectrum of 4 dB was in a range from 3.1 to 3.3 GHz with an integrated power of 1.2 W. The averaged spectral density of noise oscillations was 6 10-3 W / MHz. Efficiency of the oscillator was 15%.

Исследование тепловых процессов в мощных полевых транзисторах на основе нитрида галлия

Исследование тепловых процессов в мощных полевых транзисторах на основе нитрида галлия

Integrated Thermal Management in System-on-Package Devices

Thanks to the System-on-Package technology (SoP) the integration of different elements into a single package was enabled. However, from the thermal point of view the heat removal path in modern packaging technologies (FCBGA) goes through several layers of thermal interface material (TIM) that together with the package material create a relatively high thermal resistance which may lead to elevated chip temperature which causes functional error or other malfunctions. In our concept, we overcome this problem by creating integrated microfluidic channel based heat sink structures that can be used for cooling the high heat dissipation semiconductor devices (e.g.: processors, high power transistor or concentrated solar cells). These microchannel cooling assemblies can be integrated into the backside of the substrate of the semiconductor devices or into the system assemblies in SoP technology. In addition to the realization of the novel CMOS compatible microscale cooling device we have developed precise and valid measurement methodology, simulation cases studies and a unique compact model that can be added to numerical simulators as an external node. In this paper the achievements of a larger research are summarized as it required the cooperation of several experts in their fields to fulfil the goal of creating a state-of-the-art demonstrator.&#x0D; Thanks to the System-on-Package technology (SoP) the integration of different elements into a single package was enabled. However, from the thermal point of view the heat removal path in modern packaging technologies (FCBGA) goes through several layers of thermal interface material (TIM) that together with the package material create a relatively high thermal resistance which may lead to elevated chip temperature which causes functional error or other malfunctions. In our concept, we overcome this problem by creating integrated microfluidic channel based heat sink structures that can be used for cooling the high heat dissipation semiconductor devices (e.g.: processors, high power transistor or concentrated solar cells). These microchannel cooling assemblies can be integrated into the backside of the substrate of the semiconductor devices or into the system assemblies in SoP technology. In addition to the realization of the novel CMOS compatible microscale cooling device we have developed precise and valid measurement methodology, simulation cases studies and a unique compact model that can be added to numerical simulators as an external node. In this paper the achievements of a larger research are summarized as it required the cooperation of several experts in their fields to fulfil the goal of creating a state-of-the-art demonstrator.