High-performance Processing Units Research Articles

Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoC

FPGA-SoCs are heterogeneous embedded computing platforms consisting of reconfigurable hardware and high-performance processing units. This combination offers flexibility and good performance for the design of embedded systems. However, allowing the sharing of resources between an FPGA and an embedded CPU enables possible attacks from one system on the other. This work demonstrates that a malicious hardware block contained inside the reconfigurable logic can manipulate the memory and peripherals of the CPU. Previous works have already considered direct memory access attacks from malicious logic on platforms containing no memory isolation mechanism. In this work, such attacks are investigated on a modern platform which contains state-of-the-art memory and peripherals isolation mechanisms. We demonstrate two attacks capable of compromising a Trusted Execution Environment based on ARM TrustZone and show a new attack capable of bypassing the secure boot configuration set by a device owner via the manipulation of Battery-Backed RAM and eFuses from malicious logic.

Non-iterative parameter estimation of the 2R-1C model suitable for low-cost embedded hardware

Parameter estimation of the 2R-1C model is usually performed using iterative methods that require high-performance processing units. Consequently, there is a strong motivation to develop less time-consuming and more power-efficient parameter estimation methods. Such low-complexity algorithms would be suitable for implementation in portable microcontroller-based devices. In this study, we propose the quadratic interpolation non-iterative parameter estimation (QINIPE) method, based on quadratic interpolation of the imaginary part of the measured impedance, which enables more accurate estimation of the characteristic frequency. The 2R-1C model parameters are subsequently calculated from the real and imaginary parts of the measured impedance using a set of closed-form expressions. Comparative analysis conducted on the impedance data of the 2R-1C model obtained in both simulation and measurements shows that the proposed QINIPE method reduces the number of required measurement points by 80% in comparison with our previously reported non-iterative parameter estimation (NIPE) method, while keeping the relative estimation error to less than 1% for all estimated parameters. Both non-iterative methods are implemented on a microcontroller-based device; the estimation accuracy, RAM, flash memory usage, and execution time are monitored. Experiments show that the QINIPE method slightly increases the execution time by 0.576 ms (about 6.7%), and requires 24% (1.2 KB) more flash memory and just 2.4% (32 bytes) more RAM in comparison to the NIPE method. However, the impedance root mean square errors (RMSEs) of the QINIPE method are decreased to 42.8% (for the real part) and 64.5% (for the imaginary part) of the corresponding RMSEs obtained using the NIPE method. Moreover, we compared the QINIPE and the complex nonlinear least squares (CNLS) estimation of the 2R-1C model parameters. The results obtained show that although the estimation accuracy of the QINIPE is somewhat lower than the estimation accuracy of the CNLS, it is still satisfactory for many practical purposes and its execution time reduces to$${1 \over {45}} - {1 \over {30}}$$.

GPU-based processing of Hartmann–Shack images for accurate and high-speed ocular wavefront sensing

Hartmann–Shack aberrometry is a widely used technique in the field of visual optics but, high-speed and accurate processing of Hartmann–Shack images can be a computationally expensive/resource intensive task. While some advancements have been made in achieving high-performance processing units, they have not been specifically designed for processing Hartmann–Shack images of the human eye with Graphics Processing Units. In this work, we present the first full-Graphics Processing Unit implementation of a Hartmann–Shacksensor algorithm aimed at accurately measuring ocular aberrations at a high speed from high-resolution spot pattern images. The proposed algorithm, called PaPyCS (Parallel Pyramidal Centroid Search), is inherently parallel and performs a very robust centroid search to avoid image noise and other artifacts. This is a field where the use of Graphics Processing Units have not been exploited despite the fact that they can boost Adaptive Optics systems and related closed-loop approaches. Our proposed implementation achieves processing speeds of 380 frames per second for high resolution (1280x1280 pixels) images, in addition to showing a high resilience to system and image artifacts that appear in Hartmann–Shack images from human eyes: more than 98% of the Hartmann–Shack images, with aberrations of up to 4 μ m Root Mean Square for a 5.12mm pupil diameter, were measured with less than 0.05 μ m Root Mean Square Error, which is basically negligible for ocular aberrations.

An Analytical Perspective to Traffic Engineering in Anonymous Communication Systems

Anonymous communication systems (ACS) offer privacy and anonymity through the Internet. They are mostly free tools and are popular among users all over the world. In the recent years, anonymity applications faced many problems regarding traffic engineering methods. Even though they ensure privacy under some conditions, their anonymity will be endangered by high performance processing units. To address these issues, this study is devoted to investigating traffic-engineering methods in anonymous communication systems, and proposes an analytical view of the current issues in ACS privacy and anonymity. Our study also indicates new types of solutions for these current issues with ACS.

Design of Floor Plan based Optimized PDP Multiplier using Novel CMOS CPL Hybrid Full Adder

The power consumption has been increasingly high in high performance processing units which are capable of processing an increased amount of binary data in bytes. The Full adders are the basic building blocks of the computational units such as ALU & MAC at lower levels of Abstraction. Hence obtaining a low power adder is being the need of the hour. There are several full adders proposed over the years for low power consumption. Low power adders are mainly aimed at minimizing the number of transistors thereby minimizing the power consumption; Most of the low power full adders have the drawback of threshold voltage degradation. In this paper a Novel CMOS CPL hybrid Full adder with 18 Transistors is proposed for low power and no threshold voltage degradation in the output. The floor plan based layout will minimize the inter connection length; the reduction of interconnection metal layer length reduces the critical path delay of the Full adder. The proposed full adder requires 50% and 77% less power than the energy efficient DPL 28T and CMOS 28T full adder. A floor plan based layout is designed for 4 bit Dadda multiplier with proposed adder and its performance is compared with the Dadda multipliers designed with other existing low power adders using automatic layout. The proposed multiplier exhibit 50% less PDP than existing architecture and is suitable for high speed application. The designed structures are simulated with 45 nm CMOS technology.

VLSI implementation of a variable-length pipeline scheme for data-driven processors

A VLSI-oriented variable-length pipeline structure for data-driven processors is presented. Ordinary inline pipelines have the problem of minimizing the average total processing time through the pipeline, since subdivision of a function along the pipeline is usually optimized for the most complex operations in spite of the fact that simpler operations need fewer stages. As a solution to this problem, a variable-length pipeline scheme in which data go through only the necessary stages according to information contained within is proposed. The scheme has been implemented on a test chip to verify performance. The chip demonstrated a minimum fall-through time (data transmission time from input to output) of 14.4 ns and a data transmission rate in the pipeline of 59 megaword/s (that is, 1/16.9 ns) as a first-in first-out (FIFO) store. By modifying the data transfer control and allocating the processing functions corresponding to the data interval of 16.9 ns, this scheme is applicable as a high-performance processing unit for data-driven processors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

IMPULSE: a high performance processing unit for multiprocessors for scientific calculation

In this paper, we propose a high performance processing unit for multiprocessor systems for scientific calculations. This processing unit is called IMPULSE. IMPULSE is equipped with a hardware process control mechanism, and a powerful floating point processor and its controller. The process control method is based on the concurrent process model called the NC model. In the NC model, the processes and their communicating channels are static, and it is relatively easy to implement the interprocess communication server and process scheduler in hardware according to this model. To enhance the system performance, IMPULSE is composed of three parts, the TASK ENGINE, IPC ENGINE, and FPP ENGINE. From the results of simulations, it appears that the IPC ENGINE provides efficient process control even if the granularity of the processes is very fine.