Design of Floor Plan based Optimized PDP Multiplier using Novel CMOS CPL Hybrid Full Adder

Abstract

The power consumption has been increasingly high in high performance processing units which are capable of processing an increased amount of binary data in bytes. The Full adders are the basic building blocks of the computational units such as ALU & MAC at lower levels of Abstraction. Hence obtaining a low power adder is being the need of the hour. There are several full adders proposed over the years for low power consumption. Low power adders are mainly aimed at minimizing the number of transistors thereby minimizing the power consumption; Most of the low power full adders have the drawback of threshold voltage degradation. In this paper a Novel CMOS CPL hybrid Full adder with 18 Transistors is proposed for low power and no threshold voltage degradation in the output. The floor plan based layout will minimize the inter connection length; the reduction of interconnection metal layer length reduces the critical path delay of the Full adder. The proposed full adder requires 50% and 77% less power than the energy efficient DPL 28T and CMOS 28T full adder. A floor plan based layout is designed for 4 bit Dadda multiplier with proposed adder and its performance is compared with the Dadda multipliers designed with other existing low power adders using automatic layout. The proposed multiplier exhibit 50% less PDP than existing architecture and is suitable for high speed application. The designed structures are simulated with 45 nm CMOS technology.