High-performance Polycrystalline Silicon Research Articles

Void-Defect Location Control of Laser-Crystallized Silicon Thin Films with Hole-Pattern

High-performance low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have been developed for larger applications than flat panel displays (FPDs) such as three-dimensional integrated circuits (3D-ICs) and glass sheet computers. The crystallinity of poly-Si thin films has been the key factor determining TFTs’ performance. In this work, a void-defect location has been controlled by patterning amorphous silicon (a-Si) thin films with rectangular and square holes before crystallized by multiline continuous-wave laser beam to avoid the effect of void-defects on the TFTs’ performance. Instead of randomly appearing in the poly-Si thin films, void-defects were only observed at the backsides of the patterned holes. Interestingly, large crystal grains without void-defects were laterally crystallized at Si strips between holes. By observing the crystallinities of poly-Si thin film around the patterned holes, both the mechanism of the void formation and crystal growth based on temperature gradient was clarified.

Recycling of silicon scraps by electron beam melting coupled with directional solidification and its mechanism of impurity removal

Silicon scraps, as the by-product of solar cells, have received more and more attention for its recycling with the continuing development of the cleaner production. However, hard particles and metal impurities in the silicon scraps are always difficult to remove deeply in industry. In this paper, electron beam melting coupled with directional solidification was used to purify silicon scraps and a silicon ingot containing low impurity was obtained by simultaneous removal of hard particles and meatal impurities. It is found that the hard particles, such as SiC and Si3N4, occurred to effective collision under the action of melt convection and linked to each other as clusters. With the convection of melt, the clusters would be captured in the lower temperature zone at the bottom of crucible to become a part of the condensate shell, which was greatly beneficial to complete removal of hard particles. In the directional solidification process, the electron beam accelerated the melt convection due to its point source heating mode, and promotes the diffusion of metal impurities. Most impurities were concentrated in the center of the top of the ingot. In other purified areas, the content of Fe, Ti were less than 0.11 ppmw, respectively. Purified silicon scraps were used to manufacture high-performance polycrystalline silicon and its average minority carrier lifetime reached 6.90 μs. The results suggested that this method is feasible to achieve the recycling of silicon scraps.

Positive-Bias Temperature Instability Improvement of Poly-Si Thin-Film Transistor With HfO2 Gate Dielectric by Ammonia Plasma Treatment

In this paper, positive-bias temperature instability (PBTI) stress with different stress voltage at $T = 125~^{\circ }\text{C}$ is executed on the high-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with HfO2 gate dielectric and ammonia (NH3) plasma surface treatment. The NH3 plasma surface treatment on the poly-Si TFT with HfO2 gate dielectric can significantly decrease the threshold voltage ( $V_{\mathrm{ TH}}$ ) approximately −1.86 V, reduce the subthreshold slope (S.S.) approximately −88 mV/decade, enhance the transconductance ( $G_{m}$ ) approximately $2.4\times $ , and driving current ( $I_{\mathrm{ drv}})$ approximately 2.34. In addition, the device degradation after PBTI stress with stress voltage $V_{G} - V_{\mathrm{ TH}} = 7$ V for 1000 s at $T = 125~^{\circ }\text{C}$ can also be improved after the NH3 plasma surface treatment, such as the suppressing of $V_{\mathrm{ TH}}$ shift from 2.063 to 0.617 V, S.S. degradation quantity from 0.284 V/decade to 0.172 V/decade, and $I_{\mathrm{ drv}}$ reduction from −77% to −44%. The improvement of the PBTI of poly-Si TFTs with NH3 plasma surface treatment is attributed to the suppression of oxide charge trapping effect and the degradation of interface state density ( $N_{\mathrm{ it}}$ ) and grain boundary trap state density ( $N_{\mathrm{ GB}}$ ).

Extended-Gate pH Sensors Using Self-Aligned Four-Terminal Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors on Glass Substrate

High-performance polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) on glass substrate are applicable to high-performance and low-cost pH sensors. We previously reported on four-terminal (4T) self-aligned planar embedded metal double-gate (E-MeDG) low-temperature (LT) poly-Si TFTs on glass substrate. This device includes a metal top gate (TG) and a metal bottom gate (BG), which are fabricated from a sputtered tungsten film. The BG is embedded in the glass substrate through chemical mechanical polishing, and the TG is fabricated in a self-aligned manner to the BG by using back-surface exposure. The material of the gate dielectric is silicon dioxide (SiO2), which is deposited using plasma-enhanced chemical vapor deposition, and has a thickness of 75 and 150 nm against the TG and BG, respectively. The material of the channel region is poly-Si, which is fabricated using diode-pumped solid-state continuous-wave laser lateral crystallization. The TG and BG can be used as the drive and control gates, and vice versa. In this device, we were able to control the threshold voltage (Vth) by varying the voltage applied to the control gate, and we confirmed a high Vth controllability. This Vth controllability is applicable for pH sensors because voltage variation applied to the control gate due to a change in pH can be read as the Vthvariation of the TFTs. Therefore, the 4T self-aligned planar E-MeDG LT poly-Si TFT can be used as an extended-gate field-effect transistor (EGFET) to measure the voltage variation due to a change in pH. Thus, we performed an evaluation of pH sensors by using the 4T self-aligned planar E-MeDG LT poly-Si TFT as an EGFET. The evaluation of pH sensors was performed using a typical glass electrode, reference electrode, and pH buffer solution in addition to the 4T self-aligned planar E-MeDG LT poly-Si TFTs. The glass electrode was connected to the TG or BG of the TFTs. The reference electrode was connected to the electrode, which applied a constant voltage. The glass electrode and reference electrode were set in the pH buffer solution. In this situation, we evaluated the pH sensors by measuring the transfer characteristics of the TFTs by using another gate, which was not connected to the glass electrode, as the drive gate. In the first experiment, we connected the glass electrode to the BG and measured the transfer characteristics by using the TG as the drive gate against pH = 8.8 and pH = 4.2 buffer solutions under various reference electrode voltages. We confirmed that the transfer characteristics of the drive gate in the pH = 8.8 buffer solution shifted toward the positive direction against the characteristics in the pH = 4.2 buffer solution at every reference electrode voltage. The pH sensitivity calculated from the Vthvariation is 21.7 mV/pH, which is fairly consistent with the theoretical pH sensitivity of 25.5 mV/pH. In the second experiment, we connected the glass electrode to the TG and measured the transfer characteristics by using the BG as the drive gate against pH = 8.7 and pH = 4.8 buffer solutions at various reference electrode voltages. We confirmed that the transfer characteristics of the drive gate in the pH = 8.7 buffer solution shifted toward the positive direction against the characteristics in the pH = 4.8 buffer solution. This trend is the same as that of the top-gate drive TFT, but the pH sensitivity calculated from the Vthvariation is 76.9 mV/pH, which is larger than that of the top-gate drive TFT. In addition, its magnitude is found to be fairly consistent with the theoretical pH sensitivity of 88.8 mV/pH. We consider that the difference in pH sensitivity between the TG and BG drives is caused by the difference in thickness between the TG and BG SiO2 dielectric. We previously confirmed that the ratio of the Vthvariation against the control gate voltage variation is larger in the BG drive than in the TG drive. We consider that the difference in pH sensitivity reflects this phenomenon. Thus, the experimental results indicate that 4T self-aligned planar E-MeDG LT poly-Si TFTs can be successfully operated as pH sensors. In summary, we confirmed that 4T self-aligned planar E-MeDG LT poly-Si TFTs can be successfully operated as pH sensors. In addition, to improve the pH sensitivity of EGFETs, our experimental results indicate that the combination of the capacitance of the top and bottom gates is a significant parameter.

P-7: High Performance LTPS Thin-film Transistors using Low Cost Polycrystalline Silicon by Blue Laser Annealing

Crystallization of amorphous silicon (a-Si) to polycrystalline silicon (p-Si) by a continuous-wave blue laser diode of wavelength 445 nm is investigated for high throughput thin-film transistor applications (TFT). As the laser scan speed is changed at constant laser power, laser scanned p-Si films show three kinds of grain shape that can be distinguished according to grain growth mechanism: (1) solid phase crystallization (SPC), (2) partial melting growth (PMG), and (3) full melting growth (FMG). These three growth mechanisms are as a result of different laser irradiation time to a-Si and relative absorbed laser energy difference, therefore, they achieve different grain size and crystallinity. By using this blue laser annealing (BLA) system, we can obtain the high performance and low cost low temperature polycrystalline silicon (LTPS) TFTs with large grain size.

Fabrication of High-Performance Bridged-Grain Polycrystalline Silicon TFTs by Laser Interference Lithography

In this paper, bridged-grain (BG) low-temperature polycrystalline silicon thin-film transistors (TFTs) were fabricated. The periodic submicrometer BG structures were patterned using a maskless and large-area applicable laser interference lithography (LIL) technology, which was able to minimize extra manufacture costs of BG structures. Compared with conventional metal-induced crystallized (MIC) poly-Si TFTs, the BG-MIC TFTs involving the LIL technology exhibited reduced threshold voltage and subthreshold swing, improved ON–OFF current ratio, and suppressed leakage current and kink effect. Since the exposure energy density is one of key parameters for LIL, its relationship with device electrical performance was further investigated. It was found that when the exposure energy density was in the vicinity of 60 mJ/cm2, these BG-MIC TFTs could perform optimally without device uniformity degradation.

Bias Temperature Instabilities for High-kHfO2LTPS-TFTs With Dual Plasma Treatment

This study is the first to investigate different reliability mechanisms of high-performance low-temperature polycrystalline silicon thin-film transistors (TFTs) with a $\hbox {HfO}_{2}$ gate dielectric before and after dual plasma treatment (DPT) under various bias temperature instability (BTI) stresses. DPT samples under positive bias temperature instability (PBI) and negative bias temperature instability (NBI) stresses exhibited different degradation phenomena because of the negative polarity trapped oxide charges and positive fixed oxide charges (Si+), respectively. In addition, experimental data exhibited better reliability immunity for PBI stress than NBI stress after DPT. Furthermore, we raised the temperature to clearly observe the effect of the PBTI stress analysis for samples with and without DPT. Extracted measurement results showed distinct time evolutions of the interface state densities (Nit) for samples with and without DPT, revealing the different mechanisms of Nit generation with and without DPT. Finally, we proposed a novel reliability mechanism called the quasi reaction-diffusion model to explain the generation of $\Delta\hbox {N}_{\rm it}$ , which also explains the unclear phenomena of mobility boost.

High-performance polycrystalline silicon thin-film transistors integrating sputtered aluminum-oxide gate dielectric with bridged-grain active channel

Polycrystalline silicon thin-film transistors (TFTs) integrating sputtered Al2O3 gate dielectric with bridged-grain active channel are demonstrated. The proposed TFTs exhibit excellent device performance in terms of smaller threshold voltage, steeper subthreshold swing and higher on-current/off-current ratio. More importantly, the mobility of the proposed TFT is 5.5 times that of conventional TFTs with SiO2 gate dielectric. All of these results suggest that the proposed TFT is a good choice for low-power and high-speed driving circuits in display application.

Low-Temperature Polycrystalline Silicon Thin-Film Transistors Enhanced by Diode-Pumped Solid State Green Continuous-Wave Laser

A novel diode-pumped solid-state continuous-wave (CW) laser technology has been demonstrated for high-performance low-temperature polycrystalline silicon thin-film transistors (TFTs) fabrication. The CW laser-crystallized (CWC) poly-Si thin films indicated the excellent crystallinity with the flat surface morphology at grain boundary. Besides, the CW laser activation is a low-thermal budget process and can achieve the lower sheet resistance of 50 Ω/□ and uniformly redistributed dopant profiles. The n-channel CWC TFTs revealed the superior field-effect mobility reaching 505 cm2/V-s and the lower subthreshold swing as compared with the conventional excimer laser-crystallized ones.

High-Performance Polycrystalline-Silicon Nanowire Thin-Film Transistors With Location-Controlled Grain Boundary via Excimer Laser Crystallization

High-performance polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) are demonstrated using excimer laser crystallization to control the locations of grain boundaries two-dimensionally. Via the locally increased thickness of the amorphous-silicon (a-Si) film as the seeds, the cross-shaped grain boundary structures were produced among these thicker a-Si grids. The NW TFTs with one primary grain boundary perpendicular to the channel direction could be therefore fabricated to achieve an excellent field-effect mobility of 346 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s and an on/off current ratio of 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> . Furthermore, the grain-boundary-location-controlled NW TFTs also exhibited better reliability due to the control of grain boundary locations. This technology is thus promising for applications of low-temperature poly-Si TFTs in system-on-panel and 3-D integrated circuits.

High-performance polycrystalline silicon thin-film transistors prepared via the laser crystallization of the prepatterned channel layer on the bottom-gate structure

High-performance polycrystalline silicon thin-film transistors (TFTs) using an excimer laser crystallization of the prepatterned channel layer on the bottom-gate (BG) structure were fabricated to exhibit a field-effect mobility as high as 339cm2/Vs and an on/off current ratio of 9.5×107 with respect to 102cm2/Vs and 1.5×107 for the conventional top-gate (TG) TFTs, respectively. Such a superior performance is attributed to the cross-shaped grain boundary structure formed in the channel region owing to the two-dimensional location control of grain boundaries. Moreover, the prepatterned BG TFTs show better device-to-device uniformity than the conventional TG ones due to the manipulated grain boundaries. This technology is thus promising for the future applications of system-on-panel and three-dimension integrated circuits.

A low‐cost and reliable optical inspection system for rapid surface roughness measurements of polycrystalline thin films

AbstractExcimer laser crystallization is a well‐known industrially used technique to produce high‐performance polycrystalline silicon thin films on the commercially available inexpensive glass substrates for the development of high‐performance low temperature polycrystalline silicon thin‐film transistors in active matrix flat panel displays. A rapid optical measurement system for rapid surface roughness measurement of polycrystalline silicon thin films was developed in this study. Two kinds of thicknesses of polycrystalline silicon thin films were used to study rapid surface roughness measurements. Six different incident angles were employed for measuring surface roughness of polycrystalline silicon thin films. The results reveal that the incident angle of 20° was found to be a good candidate for measuring surface roughness of polycrystalline silicon thin films. Surface roughness (y) of polycrystalline silicon thin films can be determined rapidly from the average value of reflected direct current voltage (x) measured by the optical system developed using the trend equation of y = –8.9854x + 91.496. The maximum measurement error rate of the optical measurement system developed was less than 5.72%. The savings in measurement time was up to 83%.

High-Performance Polycrystalline Silicon Thin-Film Transistors with Two-Dimensional Location Control of the Grain Boundary via Excimer Laser Crystallization

High-performance low-temperature polycrystalline silicon (Poly-Si) thin-film transistors (TFTs) have been fabricated with two-dimensional (2-D) location-controlled grain boundaries using excimer laser crystallization (ELC). By locally increased thickness of the amorphous silicon (a-Si) film that was served as the seed crystals with a partial-melting crystallization scheme, the cross-shaped grain boundary structures were produced between the thicker a-Si grids. The Poly-Si TFTs with one parallel and one perpendicular grain boundary along the channel direction could therefore be fabricated to reach excellent field-effect mobility of 530 cm2/V-s while the conventional ones exhibited field-effect mobility of 198 cm2/V-s. Furthermore, the proposed TFTs achieved not only superior electric properties but also improved uniformity as compared with the conventional ones owing to the artificially controlled locations of grain boundaries.

High performance low temperature polycrystalline Si thin-film transistors fabricated by silicide seed-induced lateral crystallization

A novel and simple crystallization method for high performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) using Ni silicide seed-induced lateral crystallization (SILC) was proposed in this study, and it includes no additional deposition and/or etching processes that are not found in the fabrication of conventional metal-induced lateral crystallization (MILC) TFTs. The poly-Si thin films crystallized by SILC were characterized by x-ray photoelectron spectroscopy (XPS), x-ray diffraction (XRD), field emission scanning electron microscopy (FESEM), and Micro-Raman spectroscopy. The electrical properties were obtained from ID-VG transfer curves and the interface trap density was determined by Levinson plot analysis. The results show that SILC poly-Si films have lower Ni contamination, better crystallinity, and higher crystalline fraction than MILC poly-Si films. The p-channel SILC poly-Si TFTs exhibited a mobility of 66 cm2/V·s, a minimum leakage current of 3.4 × 10−11 A at VD = −5 V, a subthreshold slope of 0.85 V/dec, and a maximum on/off ratio of 5.0 × 106, all of which resulted in a high-performance device which surpassed conventional MILC poly-Si TFTs.

High-Performance Excimer-Laser-Crystallized Polycrystalline Silicon Thin-Film Transistors with the Pre-Patterned Recessed Channel

High-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been achieved using an excimer laser crystallization method on a prepatterned recessed channel (RC). Such a prepatterned RC TFT exhibited an excellent field-effect mobility of 412 cm2 V-1 s-1 and an on/off current ratio higher than 1.1×108 as compared with 125 cm2 V-1 s-1 and 2.2×107 for the conventional ones, respectively. This is attributed to the two-dimensional control of the grain boundary location and the resultant cross-shaped grain boundary structures within the recessed regions. Therefore, the prepatterned RC TFTs with only one grain boundary parallel to the channel direction as the TFTs could be fabricated to avoid the perpendicular grain boundary. This technology is thus promising for the future applications of poly-Si TFTs in the system-on-panel (SOP) and three-dimensional integrated circuits (3D-ICs).

Electrical and reliability characteristics of polycrystalline silicon thin-film transistors with high-κ Eu2O3 gate dielectrics

In this study, we developed a high-performance low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) incorporating an ultra thin Eu2O3 gate dielectric. High-κ Eu2O3 LTPS-TFT annealed at 500 °C exhibits a low threshold voltage of 0.16 V, a high effective carrier mobility of 44 cm2/V-s, a small subthreshold swing of 142 mV/decade, and a high Ion/Ioff current ratio of 1.34 × 107. These significant improvements are attributed to the high gate-capacitance density due to the adequate quality of Eu2O3 gate dielectric with small interfacial layer of effective oxide thickness of 2.5 nm. Furthermore, the degradation mechanism of positive bias temperature instability was studied for a high-k Eu2O3 LTPS-TFT device.

High-Performance Poly-Si Nanowire Thin-Film Transistors Using the $\hbox{HfO}_{2}$ Gate Dielectric

High-performance polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) using hafnium dioxide as gate dielectric is successfully fabricated for the first time. The excellent short-channel characteristics are attributed to the high- gate dielectric, ultrathin poly-Si NW channel thickness, and omega-shaped gate structure. The record high driving capability of 549 results from the ultrashort gate length , thin equivalent oxide thickness, and Ni silicide metal source/drain. This letter reveals the opportunity of high-performance poly-Si TFT circuits for system-on-panel and 3-D integrated circuit (3-D IC) applications.

High-Performance Polycrystalline Silicon TFT on the Structure of a Dopant-Segregated Schottky-Barrier Source/Drain

A high-performance polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Schottky-barrier (SB) source/drain (S/D) junctions is proposed. A p-channel operation on the intrinsic nickel (Ni) silicided S/D was successfully realized with the aid of a thin active layer, despite the fact that the Ni silicided material shows a high SB height (SBH) for holes. Furthermore, for n-channel operation, the dopant-segregation technique implemented on the intrinsic Ni silicide was utilized to reduce the effective SBH for electrons. The results show a higher on-current due to the lower parasitic resistance as well as superior immunity against short-channel effects, compared to the conventional poly-Si TFT composed of p-n S/D junctions.

Fabrication and characterization of low temperature polycrystalline silicon thin film transistors by ink-jet printed nickel-mediated lateral crystallization

High-performance polycrystalline silicon thin film transistors (poly-Si TFTs) were fabricated by using ink-jet printed nickel on large area glass substrates. Direct-printed Ni dots were used as a catalyst to crystallize the amorphous silicon into poly-Si for use in the channel region of TFT devices by metal-induced lateral crystallization. The fabricated poly-Si TFTs showed high field-effect mobility and on-off ratio that are comparable to the TFTs prepared using conventional semiconductor processes. The method presented here is a combination of bottom-up and top-down approaches and has a potential to be used in next generation high-performance poly-Si TFT fabrication.

Improved Uniformity and Electrical Performance of Continuous-Wave Laser-Crystallized TFTs Using Metal-Induced Laterally Crystallized Si Film

Continuous-wave (CW) laser crystallization (CLC) of amorphous Si (α-Si) has previously been employed to fabricate high-performance low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Unfortunately, their uniformity was poor because the shape of the beam profiles was Gaussian. In this study, α-Si film was replaced by Ni-metal-induced laterally crystallized Si (MILC-Si). MILCLC-Si was MILC-Si irradiated by a CW laser (λ ≈ 532 nm and power ≈ 3.8 W). It was found that the performance and uniformity of the metal-induced laterally crystallized continuous-wave laser crystallization - thin film transistors (MILCLC-TFTs) were much better than those of the CLC-TFTs. Therefore, the MILCLC-TFT is suitable for application in systems on panels.