High-performance Polysilicon Thin-film Transistors Research Articles

High-performance poly-silicon TFTs with high-k Y2O3 gate dielectrics

In this paper, we describe a poly-Si thin-film transistor (TFT) incorporating a high-k Y2O3 gate dielectric for different annealing times. The high-k Y2O3 poly-Si TFT device annealed in O2 gas for 60 min exhibited better electrical characteristics in terms of a high effective carrier mobility of 32.7 cm2 V−1 s−1, small subthreshold slope of 269 mV dec−1, and high Ion/Ioff current ratio of 1.83 × 107. This result is attributed to a smooth surface, structural relaxation, and a low trap-state density at the Y2O3/poly-Si interface after a long time thermal annealing. All of these results suggest that the 60 min annealed poly-Si Y2O3 TFT is a good candidate for high-performance low-temperature poly-Si TFTs.

A High-Performance Polysilicon Thin-Film Transistor Built on a Trenched Body

In this paper, a high-performance polysilicon thin-film transistor (poly-Si TFT) with a trenched body is proposed, fabricated, and studied. This new trenched TFT can be easily produced by filling and etch-back technology without destroying the channel film quality. The addition of the body trench is found to reduce the off-state leakage current by 70% on average, because the trench induces a carrier scattering effect in the poly-Si grain-boundary traps, thereby affecting the leakage path. Although the off-state current is substantially reduced, the on-state current is comparable with that of a conventional TFT. Our multiple-trenched-body TFT is also shown to improve the breakdown voltage by 11%.

Flexible microelectronics becoming a reality with Suftla transfer technology

Abstract— Suftla is a technology that is used to transfer polycrystalline silicon (polysilicon) thin‐film‐transistor (TFT) circuits from an original glass substrate to a plastic sheet. The electronic devices in the next generation will be thin, lightweight, and will handle huge amounts of data, yet consume less energy. Suftla technology, together with high‐performance polysilicon TFTs, meets all these requirements because we have developed a variety of smart flexible electronic devices, such as thin paperback‐sized displays and microprocessors. Suftla will usher in a new era of life‐enhancing flexible microelectronics.

A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions

Poly-Si TFTs with this new structure have been successfully fabricated and the results demonstrate a higher on-off current ratio of 5.9/spl times/10/sup 6/ and also shows the off-state leakage current 100 times lower than those of the conventional ones at V/sub GS/=-15 V and V/sub DS/=10 V. Only four photo-masking steps are required and fully compatible with the conventional TFT fabrication processes. This novel structure is a good candidate for the further high-performance large-area device applications.

High-performance polysilicon thin film transistors on steel substrates

We fabricated thin film transistors in polycrystalline silicon on steel substrates. The polycrystalline silicon films were made by thermally annealing hydrogenated amorphous silicon precursor films, which had been deposited on stainless steel coated with ∼0.5 μm thick 810°C-annealed SiO 2. We employed annealing temperatures ranging from 600°C, which is the furnace annealing temperature limit for conventional glass substrates, to 750°C. Films were crystallized at 650°C in 1 h with 1-h hydrogen plasma seeding, at 700°C in 10 min either with or without hydrogen plasma seeding, and at 750°C in 2 min. The best top-gate transistors were made from films crystallized at 650°C and had an average electron field-effect mobility of 64 cm 2/V s in both the linear and saturated regimes. Thus steel substrates permit a substantial reduction in crystallization time over conventional glass substrates, and produce polycrystalline silicon with an electron mobility greater than other substrates.

Low-temperature polysilicon thin-film transistors fabricated from laser-processed sputtered-silicon films

In an effort to develop a simple low-temperature high-performance polysilicon thin-film transistor (TFT) technology, we report a fabrication process featuring laser-crystallized sputtered-silicon films. This top Al-gate coplanar TFT process subjects the substrate to a maximum temperature of 300/spl deg/C, and produces devices with mobilities up to 450 cm/sup 2//Vs, on/off current ratios greater than 10/sup 7/, without using a post-hydrogenation step. We believe these results represent the highest performance TFT's to date fabricated from sputtered silicon films.

High-performance thin-film transistors fabricated using excimer laser processing and grain engineering

High-performance polysilicon thin-film transistors (TFTs) are fabricated using an excimer laser to recrystallize the undoped channel and dope the source-drain regions. Using a technique we call "grain engineering" we are able to control grain microstructure using laser parameters. Resulting polysilicon films are obtained with average grain sizes of /spl sim/4-9/spl times/m in sub-100 nm thick polysilicon films without substrate heating during the laser recrystallization process. Using a simple four-mask self-aligned aluminum top-gate structure, we fabricate TFTs in these films. By combining the grain-engineered channel polysilicon regions with laser-doped source-drain regions, TFTs are fabricated with electron mobilities up to 260 cm/sup 2//Vs and on/off current ratios greater than 10/sup 7/. To our knowledge, these devices represent the highest performance laser-processed TFTs reported to date fabricated without substrate heating or hydrogenation.

A high-performance polysilicon thin-film transistor using XeCl excimer laser crystallization of pre-patterned amorphous Si films

A high-performance polysilicon thin-film transistor (TFT) fabricated using XeCl excimer laser crystallization of pre-patterned amorphous Si films is presented. The enhanced TFT performance over previous reported results is attributed to pre-patterning before laser crystallization leading to enhanced lateral grain growth. Device performance has been systematically investigated as a function of the laser energy density, the repetition rate, and the number of laser shots. Under the optimal laser energy density, poly-Si TFT's fabricated using a simple low- temperature (/spl les/600/spl deg/C) process have field-effect mobilities of 91 cm/sup 2//V/spl middot/s (electrons) and 55 cm/sup 2//V/spl middot/s (holes), and ON/OFF current ratios over 10/sup 7/ at V/sub Ds/=10 V. The excellent overall TFT performance is achieved without substrate heating during laser crystallization and without hydrogenation. The results also show that poly-Si TFT performance is not sensitive to the laser repetition rate and the number of laser shots above 10.