High-performance Metal Oxide Semiconductor Research Articles

Modeling Interfacial Interaction between Gas Molecules and Semiconductor Metal Oxides: A New View Angle on Gas Sensing.

With the development of internet of things and artificial intelligence electronics, metal oxide semiconductor (MOS)-based sensing materials have attracted increasing attention from both fundamental research and practical applications. MOS materials possess intrinsic physicochemical properties, tunable compositions, and electronic structure, and are particularly suitable for integration and miniaturization in developing chemiresistive gas sensors. During sensing processes, the dynamic gas-solid interface interactions play crucial roles in improving sensors' performance, and most studies emphasize the gas-MOS chemical reactions. Herein, from a new view angle focusing more on physical gas-solid interactions during gas sensing, basic theory overview and latest progress for the dynamic process of gas molecules including adsorption, desorption, and diffusion, are systematically summarized and elucidated. The unique electronic sensing mechanisms are also discussed from various aspects including molecular interaction models, gas diffusion mechanism, and interfacial reaction behaviors, where structure-activity relationship and diffusion behavior are overviewed in detail. Especially, the surface adsorption-desorption dynamics are discussed and evaluated, and their potential effects on sensing performance are elucidated from the gas-solid interfacial regulation perspective. Finally, the prospect for further research directions in improving gas dynamic processes in MOS gas sensors is discussed, aiming to supplement the approaches for the development of high-performance MOS gas sensors.

High Performance P-Type Perovskite Lagao3 Thin Film Field Effect Transistor Prepared by Solution-Processed

Metal oxide semiconductor (MOS) is essential to compose high-performance electronic devices, however, the investigation on p-type MOS is relatively rare compared with its n-type counterpart. In this work, LaGaO3 thin films with superior p-type conductivity have been prepared via a facile solution process. Moreover, we have implemented Al2O3 and SiO2 as the dielectric of the p-channel LaGaO3 thin film transistors (TFTs) annealed at different temperatures. Particularly, the LaGaO3/Al2O3 TFTs annealed at 700 °C exhibit an ultrahigh hole mobility of 12.4 cm2V-1s-1, Under the same conditions, LaGaO3/Al2O3 thin film transistor is two orders of magnitude higher than LaGaO3/SiO2 thin film transistor. The advanced p-type characteristics of the LaGaO3 thin film, along with its facile low-cost fabrication process can shed new light on future design of high-performance complementary MOS circuit with other optimized facile-integrated dielectrics.

Bias Stress Stability of Solution-Processed Nano Indium Oxide Thin Film Transistor.

In this paper, the effects of annealing temperature and other process parameters on spin-coated indium oxide thin film transistors (In2O3-TFTs) were studied. The research shows that plasma pretreatment of glass substrate can improve the hydrophilicity of glass substrate and stability of the spin-coating process. With Fourier transform infrared (FT-IR) and X-ray diffraction (XRD) analysis, it is found that In2O3 thin films prepared by the spin coating method are amorphous, and have little organic residue when the annealing temperature ranges from 200 to 300 °C. After optimizing process conditions with the spin-coated rotating speed of 4000 rpm and the annealing temperature of 275 °C, the performance of In2O3-TFTs is best (average mobility of 1.288 cm2·V−1·s−1, Ion/Ioff of 5.93 × 106, and SS of 0.84 V·dec−1). Finally, the stability of In2O3-TFTs prepared at different annealing temperatures was analyzed by energy band theory, and we identified that the elimination of residual hydroxyl groups was the key influencing factor. Our results provide a useful reference for high-performance metal oxide semiconductor TFTs prepared by the solution method.

High-Sensitive MEMS Hydrogen Sulfide Sensor made from PdRh Bimetal Hollow Nanoframe Decorated Metal Oxides and Sensitization Mechanism Study.

Here we report the fabrication of a high performance metal oxide semiconductor (MOS) sensor for the detection of hydrogen sulfide (H2S) using PdRh bimetal hollow nanocube (HC) with Rh-rich hollow frame and Pd-rich core frame as sensitizing materials. PdRh bimetal HC with the edge-length about 10 nm was prepared by chemical etching PdRh bimetal solid nanocube (SC) in HNO3 aqueous solution. The results of gas-sensing tests indicate that the response value order of the MEMS gas sensors based on MOSs (including ZnO, MoO3 and SnO2) is as follows: RPdRhHC/MOS > RPdRhSC/MOS > RMOS. First, in the system of ZnO, gas sensor modified by PdRh (PdRh SC/ZnO and PdRh HC/ZnO) possess enhanced H2S sensing performance with a better response and excellent low-concentration detection capability (down to 15 ppb) comparing to pure ZnO. The improved H2S sensing performance could be attributed to the good conductivity of Rh-rich frame, the high catalytic activity of PdRh bimetal and formation of Schottky barrier-type junctions and defect. Second, PdRh HC/ZnO sensor shows better response (185-1 ppm of H2S) compared to PdRh SC/ZnO sensor (108-1 ppm of H2S), which is due to the higher specific surface area of PdRh HC/ZnO and good gas diffusion of the hollow structure. This work indicate that the sensitization characteristics of PdRh bimetal HC will provide new paradigms for the future development of the high performance sensor.

An Overview of High-k Oxides on Hydrogenated-Diamond for Metal-Oxide-Semiconductor Capacitors and Field-Effect Transistors

Thanks to its excellent intrinsic properties, diamond is promising for applications of high-power electronic devices, ultraviolet detectors, biosensors, high-temperature tolerant gas sensors, etc. Here, an overview of high-k oxides on hydrogenated-diamond (H-diamond) for metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) is demonstrated. Fabrication routines for the H-diamond MOS capacitors and MOSFETs, band configurations of oxide/H-diamond heterointerfaces, and electrical properties of the MOS and MOSFETs are summarized and discussed. High-k oxide insulators are deposited using atomic layer deposition (ALD) and sputtering deposition (SD) techniques. Electrical properties of the H-diamond MOS capacitors with high-k oxides of ALD-Al2O3, ALD-HfO2, ALD-HfO2/ALD-Al2O3 multilayer, SD-HfO2/ALD-HfO2 bilayer, SD-TiO2/ALD-Al2O3 bilayer, and ALD-TiO2/ALD-Al2O3 bilayer are discussed. Analyses for capacitance-voltage characteristics of them show that there are low fixed and trapped charge densities for the ALD-Al2O3/H-diamond and SD-HfO2/ALD-HfO2/H-diamond MOS capacitors. The k value of 27.2 for the ALD-TiO2/ALD-Al2O3 bilayer is larger than those of the other oxide insulators. Drain-source current versus voltage curves show distinct pitch-off and p-type channel characteristics for the ALD-Al2O3/H-diamond, SD-HfO2/ALD-HfO2/H-diamond, and ALD-TiO2/ALD-Al2O3/H-diamond MOSFETs. Understanding of fabrication routines and electrical properties for the high-k oxide/H-diamond MOS electronic devices is meaningful for the fabrication of high-performance H-diamond MOS capacitor and MOSFET gas sensors.

Compact conduction band model for transition-metal dichalcogenide alloys

Monolayer transition metal dichalcogenide (TMD) alloys, such as Mo1−xWxS2, owing to the unique electronic properties of the atomically thin two-dimensional layered structure, can be made into high performance metal–oxide–semiconductor field-effect transistors. The compact conduction band model of effective mass approximation (EMA) with the second nonparabolic correction is proposed for monolayer Mo1−xWxS2. The three band tight-binding (TB) method is used for calculating the band structure for monolayer TMD alloys such as Mo1−xWxS2, and a compact conduction band model is precisely developed to fit the band structures of TMD alloys calculated with tight-binding methods for the calculation of electron mobility. The impact of alloys on electron mobility of monolayer Mo1−xWxS2 is discussed in this study.

The impact of ultrathin Al2O3 films on the electrical response of p-Ge/Al2O3/HfO2/Au MOS structures

It is well known that the most critical issue in Ge CMOS technology is the successful growth of high-k gate dielectrics on Ge substrates. The high interface quality of Ge/high-k dielectric is connected with advanced electrical responses of Ge based MOS devices. Following this trend, atomic layer deposition deposited ultrathin Al2O3 and HfO2 films were grown on p-Ge. Al2O3 acts as a passivation layer between p-Ge and high-k HfO2 films. An extensive set of p-Ge/Al2O3/HfO2 structures were fabricated with Al2O3 thickness ranging from 0.5 nm to 1.5 nm and HfO2 thickness varying from 2.0 nm to 3.0 nm. All structures were characterized by x-ray photoelectron spectroscopy (XPS) and AFM. XPS analysis revealed the stoichiometric growth of both films in the absence of Ge sub-oxides between p-Ge and Al2O3 films. AFM analysis revealed the growth of smooth and cohesive films, which exhibited minimal roughness (~0.2 nm) comparable to that of clean bare p-Ge surfaces.The electrical response of all structures was analyzed by C–V, G–V, C–f, G–f and J–V characteristics, from 80 K to 300 K. It is found that the incorporation of ultrathin Al2O3 passivation layers between p-Ge and HfO2 films leads to superior electrical responses of the structures. All structures exhibit well defined C–V curves with parasitic effects, gradually diminishing and becoming absent below 170 K. Dit values were calculated at each temperature, using both Hill–Coleman and Conductance methods. Structures of p-Ge/0.5 nm Al2O3/2.0 nm HfO2/Au, with an equivalent oxide thickness (EOT) equal to 1.3 nm, exhibit Dit values as low as ~7.4 × 1010 eV−1 cm−2. To our knowledge, these values are among the lowest reported. J–V measurements reveal leakage currents in the order of 10–1 A cm−2, which are comparable to previously published results for structures with the same EOT. A complete mapping of the energy distribution of Dits into the energy bandgap of p-Ge, from the valence band towards midgap, is also reported. These promising results contribute to the challenge of switching to high-k dielectrics as gate materials for future high-performance metal–oxide–semiconductor field-effect transistors based on Ge substrates. Making the switch to such devices would allow us toexploit its superior properties.

Soft‐switched non‐isolated high step‐up DC–DC converter with reduced voltage stress

In this study, a novel soft-switched high step-up DC/DC converter is presented. This converter is suitable to be employed in photovoltaic and fuel cell systems. The proposed topology is based on coupled inductors and switched-capacitor techniques to provide high step-up gain. Also, due to high conversion ratio, and symmetrical structure of the proposed topology, the voltage stress of semiconductor elements is low; therefore, high performance metal–oxide–semiconductor field-effect transistors with low ON-resistance, and also low-voltage rating diodes can be utilised to reduce the circuit cost, conduction, and reverse-recovery losses which improve the converter efficiency and power density. Furthermore, by adopting an active clamp circuit, the stored energy in the leakage inductance of coupled inductors is recycled and zero-voltage-switching turn-on condition for both main and clamp switches are provided. Operating principle and steady-state analysis of the converter are discussed in detail. Finally, an experimental prototype of the proposed converter with 200 W output power is implemented which verifies the theoretical analysis.

Advanced photo-annealing of indium zinc oxide films for thin-film transistors using pulse UV light

An ultra-fast and simple method for forming high-performance metal oxide semiconductor by a solution process based on sol–gel condensation in ambient air using pulse ultraviolet-light annealing is proposed for the thin-film transistor (TFT) application. Even a small amount of light absorbance by the transparent metal oxide film provide sufficient energy to carry out sol–gel condensation because of the extremely high peak energy and broad irradiation spectrum of the xenon lamp used in this study. The fabricated indium zinc oxide TFTs had a field-effect mobility of 2.4 cm2 V−1 s−1, which is comparable to a device performance of 2.7 cm2 V−1 s−1 obtained through thermal annealing.

Epitaxial GeSn film formed by solid phase epitaxy and its application to Yb2O3-gated GeSn metal-oxide-semiconductor capacitors with sub-nm equivalent oxide thickness

Through the technique of solid phase epitaxy (SPE), an epitaxial Ge0.955Sn0.045 film was formed on a Ge substrate by depositing an amorphous GeSn film followed by a rapid thermal annealing at 550 °C. A process that uses a SiO2 capping layer on the amorphous GeSn film during SPE was proposed and it prevents Sn precipitation from occurring while maintaining a smooth surface due to the reduced surface mobility of Sn atoms. The high-quality epitaxial GeSn film was observed to have single crystal structure, uniform thickness and composition, and tiny surface roughness with root mean square of 0.56 nm. With a SnOx-free surface, Yb2O3-gated GeSn metal-oxide-semiconductor (MOS) capacitors with equivalent oxide thickness (EOT) of 0.55 nm were developed. A small amount of traps inside the Yb2O3 was verified by negligible hysteresis in capacitance measurement. Low leakage current of 0.4 A/cm2 at gate bias of flatband voltage (VFB)-1 V suggests the high quality of the gate dielectric. In addition, the feasibility of using Yb2O3 to well passivate GeSn surface was also evidenced by the small interface trap density (Dit) of 4.02 × 1011 eV−1 cm−2, which can be attributed to smooth GeSn surface and Yb2O3 valency passivation. Both leakage current and Dit performance outperform other passivation techniques at sub-nm EOT regime. The proposed epitaxial GeSn film along with Yb2O3 dielectric paves an alternative way to enable high-performance GeSn MOS devices.

Robustness of Sn precipitation during thermal oxidation of Ge1−xSnx on Ge(001)

The thermal robustness of Sn segregation and precipitation in epitaxial Ge1−xSnx layers on Ge(001) substrates with a Sn content greater than the equilibrium solubility limit has been investigated for applications of Ge1−xSnx in high-performance metal–oxide–semiconductor field-effect transistors (MOSFETs). Sn segregation and precipitation occur on the Ge1−xSnx surface after epitaxial growth of the Ge1−xSnx layer at 150 °C. After the thermal oxidation of the Ge1−xSnx layer below 500 °C, there are no significant decreases in the average Sn content in the Ge1−xSnx layer and no additional Sn segregation on the Ge1−xSnx surface. However, Sn precipitation occurs at the Ge1−xSnx surface during the thermal oxidation of the Ge1−xSnx layer with an average Sn content as high as 8.7% at 600 °C, causing a decrease in the Sn content in the Ge1−xSnx layer. The Sn content in the Ge1−xSnx oxide is 1.5 times greater than that observed near the Ge1−xSnx surface for the sample with a Sn content of 8.7% after the thermal oxidation at 400 to 500 °C. The capacitance–voltage characteristics of the Al/Al2O3/Ge1−xSnx/Ge MOS capacitors treated with thermal oxidation at 400 °C indicate that the slow state density increases with the Sn content. Meanwhile, the small interface state density could be achieved via thermal oxidation of the Ge1−xSnx layer, even with a high Sn content.

Estimation of step-by-step induced stress in a sequential process integration of nano-scale SOS MOSFETs with high-k gate dielectrics

The current work proposes a novel technique to incorporate process-induced uni-axial stress for significant mobility boosting in high-performance metal–oxide–semiconductor field-effect-transistors. It has been shown that two existing standard techniques, namely, silicon-on-sapphire and high-k gate dielectrics can be combined to develop such technology. Sapphire has very high elastic constant and thermal expansion coefficient, thereby capable of inducing a significant amount of stress which is observed to be biaxial in nature. However, with the incorporation of different materials during process integration, such biaxial stress is gradually changed to uni-axial nature. The high-k gate dielectric plays the key role in converting the biaxial stress to uni-axial. Several high-k gate dielectrics have been studied and titanium oxide (TiO2) is observed to maximize the induced stress and also effective to convert it to uni-axial. A final average longitudinal channel stress of 0.73 GPa has been obtained.

Improved electrical characteristics high-k gated MOS devices with in-situ remote plasma treatment in atomic layer deposition

Metal oxide semiconductor (MOS) devices with in situ remote plasma treatment during high-k dielectric deposition are studied in this work. The EOT value and leakage current of the MOS device with in situ NH3 plasma treated high-k dielectrics can be significantly reduced to 0.83 nm and 1.7 × 10−3 A/cm2, respectively. The stress-induced flat-band voltage shifts and leakage current are obviously reduced as well. In-situ remote plasma treatment also provides a good approach of nitridation for high-k dielectrics. The oxygen vacancy can be passivated by nitrogen, which suppresses further oxygen diffusion and the formation of the oxygen vacancies. The in situ NH3 plasma treatment is useful for high performance MOS devices with good reliability.

Overview of low temperature hydrophilic Ge to Si direct bonding for heterogeneous integration

Germanium is gaining interest in two important areas of electronics; for high performance metal oxide semiconductor field effect transistors due to the high carrier mobility and for imaging and optical applications due to its superior absorption in the infrared range. Optimally, germanium will be integrated with existing silicon electronics to enhance electrical and optical properties. One method for integration of germanium with silicon is direct wafer bonding of the two materials. In this paper, wafer-level germanium–silicon heterogeneous integration technologies are investigated and described in detail, including structural and electrical features of bonded hetero-structure.

Technology computer-aided design simulation study for a strained InGaAs channel n-type metal-oxide-semiconductor field-effect transistor with a high-k dielectric oxide layer and a metal gate electrode

The stress distributions in the InGaAs channel regions of strained InGaAs metal-oxide-semiconductor (MOS) field-effect transistors with high-k dielectric layer, metal gate, and InGaAs alloy souce/drain (S/D) stressors were studied with three-dimensional process simulations. It was shown that the geometric effects, such as channel width and length, could impact the achievable transistor performance gains. In this work, high-performance III-V MOS devices were achieved by stressors, such as S/D stressors, with the InGaAs alloy material. The resulting mobility improvement was analyzed by the Monte Carlo simulations. Tensile stress along the transport direction was found to dominate mobility gain while narrower devices (<1 μm), and a decrease of tensile stress along the channel direction contributed to a decrease in mobility gain owing to the decreasing width. This work helps the future III-V-based MOS device design and demonstrates that strain engineering is important for future nanoscale device technology.

Effective passivation and high-performance metal–oxide–semiconductor devices using ultra-high-vacuum deposited high- κ dielectrics on Ge without interfacial layers

Without using any interfacial passivation layers, high- κ dielectric Y 2O 3, HfO 2, and Ga 2O 3(Gd 2O 3) [GGO], by electron beam evaporation in ultra-high-vacuum (UHV), have been directly deposited on Ge substrate. Comprehensive investigations have been carried out to study the oxide/Ge interfaces chemically, structurally, and electronically: hetero-structures of all the studied oxides on Ge are highly thermally stable with annealing to 500 °C, and their interfaces remain atomically sharp. The electrical analyses have been conducted on metal–oxide–semiconductor (MOS) devices, i.e. MOS capacitors (MOSCAPs) and MOS field-effect-transistors (MOSFETs). Dielectrics constants of the Y 2O 3, HfO 2, and GGO have been extracted to be ∼17, 20, and 13–15, respectively, indicating no interfacial layer formation with 500 °C annealing. A low interfacial density of states ( D its), as low as 3 × 10 11 cm −2 eV −1, has been achieved for GGO/Ge near mid-gap along with a high Fermi-level movement efficiency as high as 80%. The GGO/Ge pMOSFETs with TiN as the metal gate have yielded very high-performances, in terms of 496 μA/μm, 178 μS/μm, and 389 cm 2/V s in saturation drain current density, maximum transconductance, and effective hole mobility, respectively. The gate width and gate length of the MOSFET are 10 μm and 1 μm.

Thermal SiO2 gated Ge metal-oxide-semiconductor capacitor on Si substrate formed by thin amorphous Ge oxidation and thermal annealing

The thermal SiO2 gated Ge metal-oxide-semiconductor (MOS) capacitor on Si substrate was accomplished by the direct oxidation of the amorphous Ge layer and a subsequent forming gas annealing. The epitaxial Ge on Si substrate shows the good crystallinity and the smooth interface with the thermal oxide. The oxide on the Ge layer is confirmed to have SiO2 bonding structure with tiny Ge content. The negligible hysteresis and the small frequency dispersion in C-V characteristics indicate the desirable oxide quality. The conduction mechanism through the oxide has been verified as Fowler–Nordheim tunneling with the conduction band offset of 2.81eV. Another intriguing point of this process lies in the fact that it provides a simpler and ultralarge scale integration-compatible approach to fabricate high-performance Ge MOS field effect transistors as compared with previous works.

Characterization of Strain for High-Performance Metal–Oxide–Semiconductor Field-Effect-Transistor

Strain evaluation in a small area is required because the extremely short channel length in state-of-the-art metal–oxide–semiconductor field-effect transistors (MOSFETs) leads to a narrow and shallow channel region. The strain in this limited area strongly affects the device performance owing to carrier mobility modification. We used UV–Raman spectroscopy with a quasi-line-shape excitation source and a two-dimensional charge-coupled-device detector in order to evaluate the strain distribution in Si or Si-on-insulator (SOI) substrates with a patterned SiNx film. As results, the strain was concentrated at the SiNx/Si interface and SiNx film pattern edge. A large tensile (compressive) strain was induced by the SiNx film with inner tensile (compressive) stress in the space region that corresponds to a channel region of the n- or p-MOSFETs. We assume that these large strains in the space region are the origin of the mobility enhancement in n- or p-MOSFETs. Furthermore, in addition to the size effect of channel length, we confirmed that the strain could be controlled by changing SiNx film thickness, film stress, and the substrate (SOI or bulk-Si). The quantitative evaluation of strain by means of simulation is also discussed.

A high-performance Si-based MOS electrooptic phase Modulator with a shunt-capacitor configuration

A novel Si-based metal-oxide-semiconductor (MOS) electrooptic phase modulator including two shunt oxide layer capacitors integrated on a silicon-on-insulator (SOI) waveguide is simulated and analyzed. The refractive index near the two gate oxide layers is modified by the free carrier dispersion effect induced by applying a positive bias on the electrodes. The theoretical calculation of free carrier distribution coupled with optical guided mode propagation characteristics has been carried out. The influence of the structure parameters such as the width and the doping level of the active region are analyzed. A half-wave voltage V/sub /spl pi//=4 V is demonstrated with an 8-mm active region length and a 4-/spl mu/m width of an inner rib under an accumulation mode. When decreasing the inner rib width to 1 /spl mu/m, the phase modulation efficiency is even higher, and the rise and fall times reach 50 and 40 ps, respectively, with a 1.0/spl times/10/sup 17/ cm/sup -3/ doping level in the active region.

Experimental determination of equivalent oxide thickness of gate insulators

We propose an experimental method of determining the equivalent oxide thickness (EOT) of gate insulators based on the principle that the capacitance associated with the bandbendings in the Si substrate and the gate (Si capacitance) depends only on the Si surface field. To do this we experimentally obtained the Si surface field by using the capacitance–voltage (CV) integration method, and we used x-ray reflectometry to measure the physical thickness of thermal oxides. We then determined the relationship between the Si capacitance and the Si surface field. The relationship among the Si capacitance, the Si surface field, the EOT, and gate voltage minus the flatband voltage was also experimentally obtained. From these two relationships, we produce ideal CV curves for any given EOT and determined EOTs in such a way that the ideal CV curves fit best with the experimental results. Accordingly, our method is free of errors that accompany modeling the quantum mechanics of the gate electrode and Si substrate, and any errors that it does contain are independent of the film thickness. We further simplified the method for practical application by approximating the above relationships using rational polynomials. The results obtained by this simplified method were in good agreement with the experiments for the whole range of thicknesses. In contrast, the conventional quantum mechanical simulators produced CV curves that showed no small difference from the measured ones in the case of thin oxides in the 1-nm-thick range, and led to an overestimate of the EOT. Our method of EOT derivation provides an important basis for developing high-performance metal–oxide–semiconductor transistors.