High-performance Logic Technology Research Articles

A comprehensive technique for estimation of process-induced fixed charges and effective work function of the metal gate on high- stack

An efficient generalized methodology is proposed for precise estimation of process-induced various fixed charge distributions in the dielectric layer and extraction of the effective work function (EWF) of the metal gate on double layer high-κ/SiO2 stack in metal-oxide-semiconductor (MOS) capacitors. Present technique is equally applicable for devices grown on multiple wafers with varying as well as uniform doping concentrations. The analysis is verified with experimentally obtained high-frequency capacitance–voltage (C–V) results by varying only the physical thickness of the high-κ dielectric layer on an interfacial silicon dioxide (SiO2) film of a fixed thickness in MOS devices fabricated using a wide variety of high-κ metal gate (HKMG) technologies including the recent advanced 28 nm high performance logic technology node. Presence of significant amount of positive bulk charges in the high-κ layer, negative fixed charges at the high-κ/SiO2 interface in addition to fixed oxide charges and interface traps at the Si/SiO2 interface are observed from our analysis. Furthermore, we have observed a negligible amount of bulk positive charges compared to the effective positive charges at the Si/SiO2 interface in TaN/SiO2/ capacitors. The present analysis applied on bi-layer gate stacks with different high-κ materials viz hafnium oxide (HfO2) and aluminum oxide (Al2O3) and also on single layer SiO2 dielectric processed under various conditions, reveals that RTA in N2 results nitrogen related negative oxide charges at the Si/SiO2 interface. However, annealing in N2 has no significant effect on reduction of number of interface traps at the Si/SiO2 interface.

On the C-V characteristics of nanoscale strained gate-all-around Si/SiGe MOSFETs

Gate-all-around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs) is one of the mainstream research topics of the current era in the field of semiconductor devices since they are the most efficient architectures among all multiple-gate (MG) devices. Incorporating strain in GAA device can boost the device performance significantly. As such, strained-Si (S-Si) GAA MOSFETs can have vast technological importance in future high performance logic technologies. Due to imperfections in the fabrication process, the cross-section of a GAA device may deviate from its ideal circular nature, giving rise to an elliptical structure. Capacitance-Voltage (C-V) characteristics is an important tool for characterizing such devices. For the first time, we analytically model the quasi-static C-V characteristics of elliptical S-Si GAA MOSFETs for various operating regions. We have incorporated quantum mechanical effects (QMEs) which cannot be neglected in devices having ultra-nanometre dimensions. Computations were carried out to investigate the effects of device dimensions, interface trap charges, doping concentration, germanium mole fraction and stress on the C-V characteristics of S-Si GAA MOSFETs. The possibilities for enhancing the device performance by using high-k dielectrics have also been investigated.

(Keynote) Contemporary and Future Logic Devices

Headwinds faced by scaling efforts of high performance logic technology have forced engineering teams to go beyond dumb shrinking of device dimensions and into clever employment of new materials and structures, over last few technology nodes. We departed technology staple, planar transistors, and entered into 3D structures, half a dozen years ago. Such paradigm shifts will continue to happen more often in the years to come. We will look at today's state-of-the-art devices - FinFETs - and explore capability and suitability of new architectures for years to come. Those include variants of gate-all-around (GAA) transistors, horizontal and vertical, negative-capacitance FET (NCFET), tunnel FET (TFET), and spin-based devices. We'll assess feasibility of material contenders for better channel transport - III-V, SiGe/Ge, carbon nanotubes (CNT) and 2D transition metal di-chalcogenides (TMD). Finally, we discuss 3D monolithic device stacking and standard cell level design-technology co-optimization role in scaling.

Representation of type I heterostructure junctionless tunnel field effect transistor for high-performance logic application

In this paper, a gate-all-around junctionless tunnel field effect transistor (JLTFET) based on heterostructure of compound and group III–V semiconductors is introduced and simulated. In order to blend the high tunneling efficiency of narrow band gap material JLTFETs and the high electron mobility of III–V JLTFETs, a type I heterostructure junctionless TFET adopting Ge–AlxGa1−xAs–Ge system has been optimized by numerical simulation in terms of aluminum (Al) composition. To improve device performance, we considered a nanowire structure, and it was illustrated that high-performance logic technology can be achieved by the proposed device. The optimal Al composition founded to be around 20 % (x = 0.2). The numerical simulation results demonstrate that the proposed device has low leakage current IOFF of ~1.9 × 10−17, ION of 4 µA/µm, ION/IOFF current ratio of 1.7 × 1011 and subthreshold swing SS of 12.6 mV/decade at the 40 nm gate length and temperature of 300 K.

Design Optimization of a Type-I Heterojunction Tunneling Field-Effect Transistor (I-HTFET) for High Performance Logic Technology

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field- effect transistor (I-HTFET) adopting Ge-AlxGa1-xAs- Ge system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2). Index Terms—Tunneling field-effect transistor (TFET), Type-I heterojunction, narrow bandgap material, high mobility, simulation, nanowire, high performance (HP) logic technology

Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High- $\kappa$/Metal-Gate nFinFETs for High-Performance Logic Applications

Strained-silicon-on-insulator (SSOI) undoped-body high-κ /metal-gate n-channel fin-shaped field-effect transistors (nFinFETs) at scaled gate lengths and pitches (i.e., <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GATE</sub> ~ 25 nm and a contacted gate pitch of 130 nm) were fabricated using a gate-first flow. A “long and narrow” fin layout (i.e., fin length ~ 1 μm) was leveraged to preserve uniaxial tensile strain in the transistors. These devices exhibit drive currents suitable for high-performance logic technology. The change in the slope of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GATE</sub> (dR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /dL <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GATE</sub> ), transconductance <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MSAT</sub> , and injection velocity ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inj</sub> ) measurements indicate a ~ 15% mobility-induced <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> enhancement with SSOI relative to SOI nFinFETs at ultrashort gate lengths. Raman measurements conducted on SSOI substrates after fin formation demonstrate the preservation of ~ 1.3-GPa uniaxial tensile strain even after 1100°C annealing.

Computer Design of Source/Drain Extension Region Profile and Spacer Length in Tri-Gate Body-Tied Fin Field-Effect Transistors with High-k Gate Dielectrics

The influences of source/drain extension region engineering and high-k gate dielectrics on the device performance of tri-gate body-tied fin field-effect transistors (FinFETs) was investigated to achieve the International Technology Roadmap for Semiconductor (ITRS) projections for high-performance (HP) logic technology. The impact of lateral source/drain doping gradient (Ldg) and spacer length (Lsp) on short-channel effects (SCEs) was extensively analyzed by three-dimensional device simulation. Results show that a lateral doping gradient along with an appropriate spacer length not only can effectively control SCEs, resulting in a low off-current, but also can be optimized to achieve low values of intrinsic gate delay and high values of on-current. The ratio of spacer length to lateral doping gradient (Lsp/Ldg) between 2.7 and 4 is optimal for achieving a low intrinsic gate delay, a low off-current, and a high on/off-current ratio. The present work provides valuable design guidelines in the performance of tri-gate body-tied FinFETs with optimal source/drain extension region engineering and serves as a tool for optimizing important device and technological parameters.

Approaching Optimal Characteristics of 10-nm High-Performance Devices: A Quantum Transport Simulation Study of Si FinFET

We utilized a fully self-consistent quantum mechanical simulator based on the contact block reduction (CBR) method to optimize a 10 nm FinFET device and meet the International Technology Roadmap for Semiconductors (ITRS) projections for double-gate high-performance logic technology devices. We found that the device ON-current approaching the value projected by the ITRS can be obtained using a conventional unstrained Si channel and a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate insulator. We also performed a detailed analysis of the gate leakage under different bias conditions. Our simulation results show that the quantum mechanical effects significantly enhance the intrinsic switching speed of the device. In our simulations, quantum confinement in both the gates and the channel has been taken into account self-consistently. The obtained theoretical value of the intrinsic switching speed for the considered FinFET device exceeds the ITRS-projected value.

Can silicon FinFETs satisfy ITRS projections for high performance 10 nm devices?

We utilize a fully self-consistent quantum mechanical simulator based on CBR method to optimize 10 nm FinFET devices to meet ITRS projections for High Performance (HP) logic technology devices. Fin width, gate oxide thickness, and doping profiles are chosen to reflect realistic values. We find that the device on-current approaching the value projected by ITRS for HP devices can be obtained using unstrained conventional (Si) channel. Our simulation results also show that quantum nature of transport in ultra small devices significantly enhances the intrinsic switching speed of the device. In addition, small signal analysis has been performed. Sensitivity of device performance to the process variation at room temperature has also been investigated.

Junction formation and its device impact through the nodes: From single to coimplants, from beam line to plasma, from single ions to clusters, and from rapid thermal annealing to laser thermal processing

The fundamental design goals for a high-performance logic technology, maximizing speed while minimizing power, drive the design of the junctions and in turn the requirements on dopant placement and activation. In the early nodes implant energies of tens of keV and furnace anneals sufficed. Scaling into the deep submicron regime brought transient enhanced diffusion to the forefront and necessitated its control. This gave rise to rapid thermal annealing and low energy implants. The requirements of current high-performance logic technologies can only be satisfied with careful defect engineering and a further reduction in thermal budget at increased annealing temperatures: flash or laser annealing. Those almost diffusionless anneals make implant precision, such as angle control, imperative. Simultaneously, productivity requirements of implanters add molecular clusters to the list of implant species and lead for certain applications to a switch from beam line to plasma implantation.

The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology

We propose selective scaling of device footprint for 65 nm and beyond CMOS technologies. The benefits of selective scaling of device footprint are illustrated using an ultrathin-body fully depleted silicon-on-insulator transistor as an example. We study the effect of footprint scaling on device, circuit, and system level performance. A complete 2D device structure is modeled for the numerical analysis. The results predict that an optimal footprint design can provide 30% smaller chip layout area, 20% faster speed, and 10% less dynamic power on overall chip performance benchmarked with a 53-bit pipelined multiplier. The variability analysis on both dc and ac characteristics indicates that the benefits of selective footprint scaling are not degraded by device variation

The quest of porous ELK materials for high performance logic technologies

To meet the demand of lower interconnect delay, using lower dielectric constant material for BEOL is an inevitable choice for 65 nm and below high performance technology nodes. Porous low k material with k < 2.7 is required for this application. However, with its porous characteristics and inferior mechanical properties, maintaining a low post process effective dielectric constant ( k process) and meeting process and packaging reliability specifications are the major challenges to the successful integration of the material [M.S. Liang, in:Challenges in Cu/Low- K Integration, IEDM, 2004.]. Proper choice of the integration scheme [C.H. Yao et al., in: Porous ULK Process Technology Development for 65/45 nm Nodes, VMIC, 2005.] and careful adjustment of its associated individual processes are the first step for maintaining the k process and keeping the process away from latent damages to reliability. Trench First Hard Mask (TFHM) and Via First integration schemes were compared for the purpose [S.S. Lin et al., in: An Optimized Integration Scheme for 0.13 m Technology Node Dual-Damascene Cu Interconnect, IITC, 2000.]. In order to characterize the process window of the integration scheme, a systematical and statistical method (Structural Design Rule, SDR, calculation) is used with supplement of an innovative in-line e-beam inspection technique, Grey Level Measurement [M.D. Lei et al., in: In-line Semi-electrical Process Diagnosis Methodology for Integrated Process Window Optimization of 65 nm and below Technology Nodes, SPIE, 2006.] combined with a specially designed test pattern (Addressable Defect Array), which covers all densities/pitches/widths of vias/trenches. These methods and techniques help us to reach the optimal process window in a methodological and timely fashion. In addition, to overcome the inherent mechanical weakness of the porous low k material, extensive finite element modeling is used to design and define mechanically stronger structures for better die saw immunity and package robustness of various packaging requirements [T.C. Huang et al., Wire Bonding Failure Mechanisms and Simulations of Cu Low- K IMD Chip Packaging, AMC 2002.]. FEM technique is also used for the reliability robustness design and derivation of design rule constraints for meeting electro-migration and stress migration requirements. [T.C. Huang et al., in: Numerical Modeling and Characterization of the Stress Migration Behavior Upon Various 90 Nanometer Cu/Low k Interconnects, IITC, 2003.] With these innovative techniques and methodologies to overcome most of obstacles, ELK application for high performance logic technologies can be developed.

Physics of process induced uniaxially strained Si

Uniaxial process induced stress is being adopted in all 90, 65, and 45 nm high performance logic technologies. The uniaxial stress offers large performance improvement at low cost and minimally increased manufacturing complexity and is scalable to future technology nodes. The mobility enhancement is larger for uniaxial than biaxial stress and can be understood from the strain altered band structure.

Weighing in on logic scaling trends

In this paper, scaling trends and the associated challenges are discussed from the perspective of the 2001 International Technology Roadmap for Semiconductors (ITRS) for both high-performance and low-power logic technologies. Starting from the overall chip circuit requirements, MOSFET and front-end process integration technology requirements, scaling trends, and challenges are discussed, as well as some of the key potential solutions to the challenges, along with the long-term issues and possible solutions for mobility improvement and optimal scaling for very small transistors. Potential solutions include eventual use of high-k gate dielectrics, metal gate electrodes, and perhaps nonclassical MOSFET devices such as double-gate SOI.

A loadless CMOS four-transistor SRAM cell in a 0.18-μm logic technology

This paper presents a loadless CMOS four-transistor (4T) cell for very high density embedded SRAM applications. Using 0.18-/spl mu/m CMOS technology, the memory cell size is 1.9344 /spl mu/m/sup 2/ (1.04 /spl mu/m/spl times/1.86 /spl mu/m), which is 35% smaller than a six-transistor (6T) cell using the same design rule. The newly developed CMOS 4T-SRAM cell operates with high stability at 1.8 V, even though its designed cell ratio is 1.0 to minimize the area. A pair of pMOS transfer transistors is used to store and retain full-swing signals in the cell without a refresh cycle. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load.

Advancing the state of the art in high-performance logic and array technology : K. H. Brown, D. A. Grose, R. C. Lange, T. H. Ning and P. A. Totta. IBM Journal of Research and Development, 36(5), 821 (1992)

Advancing the state of the art in high-performance logic and array technology : K. H. Brown, D. A. Grose, R. C. Lange, T. H. Ning and P. A. Totta. IBM Journal of Research and Development, 36(5), 821 (1992)

Advancing the state of the art in high-performance logic and array technology

Advancing the state of the art in high-performance logic and array technology