High Performance Image Processing Systems Research Articles

ALMARVI System Solution for Image and Video Processing in Healthcare, Surveillance and Mobile Applications

ALMARVI is a collaborative European research project funded by Artemis involving 16 industrial as well as academic partners across 4 countries, working together to address various computational challenges in image and video processing in 3 application domains: healthcare, surveillance and mobile. This paper is an editorial for a special issue discussing the integrated system created by the partners to serve as a cross-domain solution for the project. The paper also introduces the partner articles published in this special issue to discuss the various technological developments achieved within ALMARVI spanning all system layers, from hardware to applications. We illustrate the challenges faced within the project based on use cases from the three targeted application domains, and how these can address the 4 main project objectives addressing 4 challenges faced by high performance image and video processing systems: massive data rate, low power consumption, composability and robustness. We present a system stack composed of algorithms, design frameworks and platforms as a solution to these challenges. Finally, the use cases from the three different application domains are mapped on the system stack solution and are evaluated based on their performance for each of the 4 ALMARVI objectives.

Polish electronics in high energy physics & aerospace technology

Department of Microelectronics and Computer Science of Lodz University of Technology has high expertise in the field of design of electronic and microelectronic systems for wide range of applications. DMCS design teams participated in large number of national and international scientific research programs, grants and commercial contracts. Many of these works resulted in an introduction of new systems into scientific installations or putting new product into general markets. The paper presents selected works focused on aspects of research on accelerator control systems for high energy physics, nuclear fusion based new energy sources and design of integrated electronics for space applications. Full Text: PDF References http://tesla.desy.de DirectLink D. Makowski, et al., Solid state neutron detector system, Germany, Switzerland, France, European Patent Office, Patent no 05011654.0-1240, EP20050011654. DirectLink W. Giergusiewicz, W. Jalmuzna, K. Pozniak, N. Ignashin, M. Grecki, et al., Low latency control board for LLRF system: SIMCON 3.1, Proc. SPIE 5948, Photonics Applications in Industry and Research (2005). CrossRef D. Makowski, A. Mielczarek, P. Perek, A. Napieralski, L. Butkowski, J. Branlard, M. Fenner, H. Schlarb, and B. Yang, High-Speed Data Processing Module for LLRF, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 62, NO. 3, JUNE (2015). CrossRef K. Przygoda, T. Poźniak, A. Piotrowski, D. Makowski, G. Jabłoński, A. Napieralski, Prototype Control System for Compensation of Superconducting Cavities Detuning Using Piezoelectric Actuators, IEEE Transactions on Nuclear Science, vol. 56, no. 4, pp.2336–2340, Aug. (2009). CrossRef D. Makowski, et al., Interfaces and Communication Protocols in ATCA-Based LLRF Control Systems, IEEE Transactions on Nuclear Science, vol.56, no.5, pp.2814-2820, Oct. (2009). CrossRef D. Makowski, et al., Prototype Real-Time ATCA-Based LLRF Control System, IEEE Transactions on Nuclear Science, vol. 58, no. 4, pp. 1553–1561, Aug. (2011). CrossRef D. Makowski, et al., High-Performance Image Acquisition and Processing System with MicroTCA.4, IEEE Transactions on Nuclear Science, vol. 62, no. 3, pp. 925–931, June (2015). CrossRef G. Jabłoński, et al., IEEE 1588 Time Synchronization Board in MTCA.4 Form Factor, IEEE Transactions on Nuclear Science, vol. 62, no. 3, pp. 919–924, June (2015). CrossRef S. Simrock, at all, Maturity assessment of ITER diagnostics plant instrumentation and control design, Fusion Engineering and Design, pp. 952-956, (2015). CrossRef K. Skup, P. Orleański, W. Nowosielski, M. Jankowski, G. Jabłoński, Ł. Starzak, M. Szermer Michał, A. Napieralski, R. Darakchiev, M. Mroczkowski, Mixed Signal ASIC Controller for Satellite Medium Power DC/DC Converters, Proc. Conf. "Mixed Design of Integrated Circuits and Systems". Poland, Toruń, pp. 359-363, (2015). CrossRef K. R. Skup, P. Grudziński, P. Orleański, Application of Digital Control Techniques for Satellite Medium Power DC –DC Converters, Int. Journal of Electronics and Telecommunications, pp. 77 83, 2011. CrossRef M. Brown, Power Sources and Supplies: World Class Designs, Newnes, (2007). DirectLink M. Santos, C. Pires, J. Guilherme, N. Horta, Overview of Radiation Effects and Design Constraints off Fully Custom SMPS, IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, pp. 372 375, (2008). CrossRef L. Balogh, A Practical Introduction to Digital Power Supply Control, Power Supply Design Seminar 2004/05, (2005). DirectLink

Context-based image acquisition from memory in digital systems

A key consideration in the design of image and video processing systems is the ever increasing spatial resolution of the captured images, which has a major impact on the performance requirements of the memory subsystem. This is further amplified by the facts that the memory bandwidth requirements and energy consumption of accessing the captured images have started to become the bottlenecks in the design of high-performance image processing systems. Inspired by the successful application of progressive image sampling techniques in various image processing tasks, this work proposes the concept of Context-based Image Acquisition for hardware systems that efficiently trades image quality for reduced cost of the image acquisition process. Based on the proposed framework, a hardware architecture is developed which alters the conventional memory access pattern, to progressively and adaptively access pixels from a memory subsystem. The sampled pixels are used to reconstruct an approximation to the ground truth, which is stored in a high-performance image buffer for further processing. An instance of the architecture is prototyped on an FPGA and its performance evaluation shows that a saving of up to 85 % of memory accessing time and 33 %/45 % of image acquisition time/energy are achieved on a set of benchmarks while maintaining a high PSNR.

Machine Learning for Computer-aided Diagnosis.

Machine learning algorithms are to analyze any dataset to extract data-driven model, prediction rule, or decision rule from the dataset. Various machine learning algorithms are now used to develop high-performance medical image processing systems such as computer-aided detection (CADe) system which detects clinically significant objects from medical images and computer-aided diagnosis (CADx) system which quantifies malignancy of manually or automatically detected clinical objects. In this paper, we introduce some applications of machine learning algorithms to the development of medical image processing system.

High-Performance Image Acquisition and Processing System with MTCA.4

Fast evolution of high-performance cameras in recent years has made them promising tools for observing transient and fast events in large-scale scientific experiments. Complex experiments, such as ITER, take advantage of high-performance imaging system consisting of several fast cameras working in the range of visible and infrared light. However, the application of such devices requires a usage of high-performance data acquisition systems able to read and transfer large amount of data, reaching even 10 Gbit/s for a single camera. The MTCA.4 form factor fulfils the requirements of demanding imaging systems. The paper presents a first implementation of a complete image acquisition system built on the basis of MTCA.4 architecture, which is dedicated for the operation with high-resolution fast cameras equipped with Camera Link interface. Image data from the camera are received by the frame grabber card and transmitted to the host via the PCIe interface. The modular structure of MTCA.4 architecture allows connecting several cameras to a single MTCA chassis. The system can operate in two modes: with internal CPU installed in the MTCA chassis or with external CPU connected to the chassis with PCIe link. The usage of the external CPU opens a possibility to aggregate data from different subsystems. The system supports precise synchronization with the time reference using Precise Timing Protocol (IEEE 1588). The timing modules ensure clock distribution and triggers generation on backplane lines. These allow synchronization of image acquisition from different cameras with high precision. The software support for the system includes low-level drivers and API libraries for all components and a high-level EPICS-based environment for system control and monitoring.

FPGA + DSP-Based Real-Time Image Acquisition System Research and Design

Image processing system to calculate the volume, real-time high and the requirements of small size, using the DSP-based processor, FPGA approach, supplemented by the processor design of a high-performance real-time image processing system, and the system In the process of image acquisition and transmission of noise, using the PCB's anti-jamming design. Practice shows that two chips using FPGA + DSP, the algorithm is divided into two parts by the FPGA and DSP processing; effectively improve the efficiency of the algorithm. System real-time high, adaptability, real-time image acquisition system can meet the design requirements.

Three-dimensional image processing VLSI system with network-on-chip system and reconfigurable memory architecture

In this paper, we propose new RAM/ROM module system with reconfigurable memory architecture for three-dimensional (3D) image processing VLSI system. To enable flexible image data processing, suitable input/output data control is critical feature for high performance image processing system. The fast speed 3D VLSI system also requires efficient pipeline data operation. New RAM/ROM synthesis design system is realized by specific arrangement with RAM, ROM, pin and interconnection. The pipeline Flip- Flop control, clock buffer insertion and critical signal route have been improved to enhance whole system operation speed. The network-on-chip system is also proposed to enable fast signal transmission and correct control operation. The 3D image processing VLSI system can also be improved by suitable data storage and pipeline control flow. The chip simulation experiments show the accurate results with 247.728mW power consumption and 50MHz processing frequency. Practical chip test conclusion confirms that new RAM/ROM synthesis design can successfully realize innerchip write/read function and efficient data flow control to improve 3D reconfigurable system efficiency. Better image VLSI system can be realized by elaborate network-on-chip system and precise 3D stacking layer design.

Fine grain pipeline systems for real-time motion and stereo-vision computation

Image processing systems require high computational load that motivates the design of specific hardware architectures in order to arrive at real-time platforms. We adopt innovative design techniques based on the intensive utilisation of the inherent parallelism available on devices based on reconfigurable hardware. We customise fine-grain pipelining and superscalar units to implement specific computing architectures for motion and stereo-vision computing circuits. This high parallelism level allows us to achieve a high data throughput (one pixel feature estimation per clock cycle). This paper extensively uses these techniques for designing high performance image processing systems which fit early cognitive vision models specifications. Furthermore, it highlights the necessity of on-chip integration mechanisms, since the data throughput (bandwidth requirements) of the full system requires a very large bandwidth.

A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing

For real-time image-processing applications, a highly parallel system that exploits parallelism is desirable. A content addressable memory (CAM), or an associative processor, that can perform various types of parallel processing with words as the basic unit is a promising component for creating such a system because of its suitability for LSI implementation. Conventional CAM LSI's, however, have neither efficient function nor enough capacity for pixel-parallel processing. This paper describes a fully parallel 1-Mb CAM LSI. It has advanced functions for processing various pixel-parallel algorithms, such as mathematical morphology and discrete-time cellular neural networks. Moreover, since it has 16-K words, or processing elements (PEs), which can process 128/spl times/128 pixels in parallel, a board-sized pixel-parallel image-processing system can be implemented using several chips. A chip capable of operating at 56 MHz and 2.5 V was fabricated using 0.25-/spl mu/m full-custom CMOS technology with five aluminum layers. A total of 15.5 million transistors have been integrated into a 16.1/spl times/17.0 mm chip. Typical power dissipation is 0.25 W. Processing performance of various update and data transfer operations is 3-640 GOPS. This CAM LSI will make a significant contribution to the development of compact, high-performance image-processing systems.

A linear array processor with dynamic frequency clocking for image processing applications

The need for high-performance image processing systems has led to the design and development of several application-specific parallel processing systems. An SIMD linear array processor with dynamic frequency clocking is proposed for real-time image processing applications. The architecture uses a novel concept called dynamic frequency clocking which allows the processor to vary the clock frequency dynamically based on the operation being performed. A VLSI chip based on the proposed architecture has been designed and verified using the Cadence design tools. The chip will operate at between 400 and 50 MHz based on the operation being performed. Several low-level image processing tasks have been mapped onto the architecture to evaluate the system performance and to demonstrate the effectiveness of the dynamic frequency clocking scheme.

パーソナル・コンピュータを応用した高性能画像処理システム

パーソナル・コンピュータを応用した高性能画像処理システム