Abstract
Image processing systems require high computational load that motivates the design of specific hardware architectures in order to arrive at real-time platforms. We adopt innovative design techniques based on the intensive utilisation of the inherent parallelism available on devices based on reconfigurable hardware. We customise fine-grain pipelining and superscalar units to implement specific computing architectures for motion and stereo-vision computing circuits. This high parallelism level allows us to achieve a high data throughput (one pixel feature estimation per clock cycle). This paper extensively uses these techniques for designing high performance image processing systems which fit early cognitive vision models specifications. Furthermore, it highlights the necessity of on-chip integration mechanisms, since the data throughput (bandwidth requirements) of the full system requires a very large bandwidth.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: International Journal of High Performance Systems Architecture
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
