High-performance Digital Signal Processing Research Articles

Small Solid-Model Rocket Design and Soft Landing Trajectory Planning

A recoverable rocket is one of the keys to reusable launch technology. Currently, most recoverable rockets are powered by liquid engines, which are costly and complex compared to solid engines. In this paper, we perform soft landing trajectory planning for the designed solid rocket. First, a small model rocket equipped with a landing engine is innovatively designed. Second, a six-degree-of-freedom motion model of the rocket is established, and a minimum-landing-error problem is formed based on the landing engine. Third, successive convexification algorithm is applied to solve it. In the algorithm, a method of quaternion constraint correction is proposed to avoid the infeasibility of the problem. Lastly, the correctness and robustness of the algorithm are verified via three simulations. The possibility of rapid trajectory generation is verified by code optimization on a high-performance digital signal processor.

Research and Design of Arc Welding Parameters Control and Environment Monitoring System Based on DSP

In the process of the welding operation, a large number of welding smoke, toxic gas, and other pollutants will be produced, which can cause a variety of respiratory diseases. Therefore, the welder’s health is affected and the atmospheric environment is polluted. To monitor the detrimental soot substances produced in the arc welding process, an arc welding parameters control and environmental monitoring system was built by taking high-performance DSP (Digital Signal Processor) TMS320F2812 as the control core, which uses wireless communication technology. Multi-information sensing and welding parameters control can be carried out through the system in the arc welding process. The concentration of welding smoke, harmful gas, and other substances in the arc welding environment can be monitored in real time and the real-time environmental conditions are displayed visually. The functions of audible and visual alarms, automatic ventilation, and telecommunication are provided by the system. A lot of experimental verification and debugging results show that parameters control in the arc welding process and the monitor welding environment in real time could be realized by the built system and is running well.

Review on optical visual sensor technology

视觉传感是人类感知外界、认知世界的主要途径，研究表明人类获取的外界信息大约有80%来自于视觉。作为感知外界信息的“电子眼球”，视觉传感器是消费电子、机器视觉、安防监控、科学探测和军事侦察等领域的核心器件。近年来视觉传感器技术发展迅速，不同类型的传感器从不同维度提供丰富的视觉数据，不断增强人类感知与认知能力，视觉传感器研究工作具有重要的理论与应用需求。本报告以典型光学视觉传感器技术为主线，通过综合国内外文献和相关报道，从CCD图像传感器、CMOS图像传感器、智能视觉传感器以及红外图像传感器等研究方向，梳理论述近年来光学视觉传感器技术的发展现状、前沿动态、热点问题和趋势。;Visual sensing technique is essential for human to perceive and understand the world around them. An electronic eyeball can be melted into outdoor-related visual information, and visual sensors are equipped with such domains like consumer electronics, machine vision, surveillance, and academic researches. Visual sensor technology-based multiple sensors can be used to richer multi-dimension visual data, which can enhance human-related perceptive and cognitive ability. This literature review is focused on the growth of optical visual sensor technology, including such image sensors in relevance to CCD, CMOS, intelligent-visual, and infrared-context. The CMOS image sensor chip is produced in terms of CMOS technology, in which image acquisition unit and signal processing unit can be integrated into the same chip. It can be massproduced to a certain extent. Cost-effective applications can be oriented to such aspects in related to small size, light weight, low cost and low power consumption. With the rapid development of autonomous driving, intelligent transportation, machine vision and other fields, multi-functional and intelligent CMOS image sensors with small size will become the focus of research. The emerging CCD sensor technology and its applications have been facilitating as well. The potentials of CCD image sensor can be applied for such domains in related to remote sensing, astronomy, low light detection. In the future, the multi-spectral TDI CCD architecture based on CCD and CMOS fusion technology will be widely used. Infrared image sensor is configured and set that infrared radiation detection can be converted into physical quantity. The high-performance digital signal processing function can be integrated on the infrared focal plane. The newly infrared image sensor can be focused on larger array, higher resolution, wider spectrums, more flexible sensitivity, multi-band, and system-level chip further.

Friction-free approach for a servo system: Design of a robust sliding-mode control based on a recurrent fuzzy neural network

Uncertainties such as disturbance and nonlinear friction always exist in physical motion control systems and degrade the precision of their tracking performance. In this research, a practical control strategy is integrated with a continuously differentiable friction model for a high-performance AC servo motor that performs with a continuous control input and is, hence, more properly suited for industrial applications. To further lessen the external disturbance and improve the tracking accuracy, a recurrent fuzzy neural network scheme was developed to approximate the system uncertainties, and its stability was guaranteed by the design of robust laws. The proposed controller was implemented on a high-performance digital signal processor (TMS320C6727). The results of the tracking simulations and experiments show that the proposed control scheme has a feasible and effective design for engineering servo system. In comparison with other algorithms, our approach has smaller values for both the peak and the root mean square of the tracking error while maintaining friction compensation, and it can potentially have a software implementation.

A Low-Cost, High-Performance Digital Signal Processor (DSP) for Audio Applications

Digital audio signal processing has become increasingly common in multimedia systems as a result of the development of general-purpose digital signal processors (DSP processors) and high-precision oversampling analog-to-digital (A/D) converters. Nevertheless, the solution based on standard DSP chips could be too expensive and power-hungry for portable and home entertainment audio systems. As a result, it is necessary to locate an alternative solution that is both low-cost and low-power. In the context of digital audio applications, this paper will describe how a DSP (Digital Signal Processor) is created, as well as how its architecture functions. The proposed digital signal processor (DSP) has six stages of pipeline with a fixed 24-bit data format, and each stage has 125 instructions. The instructions for the audio signal processing are provided in a very specific manner. Each and every command is handled within the confines of a single cycle.

Efficient digital waveguide synthesis of a pipe organ

The modern pipe organ can have as many as 10 000 pipes, each of which is a simple sound generator. In order to digitally synthesize a pipe organ, each pipe requires its own digital waveguide model due to its individual geometry and state. To complicate the matter, pipe geometry can vary greatly across different pipe organ ranks, pipes can be reed-driven or air-jet-driven, and it is possible for a single key to sound many ranks at once. As a result, developing an acoustic model of even a small pipe organ is intensive both in the modeling and in the computational demands for real-time synthesis. For modeling the pipes, we propose a scalable lossy digital waveguide framework whose parameters can be changed based on a pipe's geometric model. We utilize the Faust functional programming language to produce high-performance digital signal processing code.

A Review of Self-Coherent Optical Transceivers: Fundamental Issues, Recent Advances, and Research Directions

This paper reviews recent progress on different high-speed optical short- and medium-reach transmission systems. Furthermore, a comprehensive tutorial on high-performance, low-cost, and advanced optical transceiver (TRx) paradigms is presented. In this context, recent advances in high-performance digital signal processing algorithms and innovative optoelectronic components are extensively discussed. Moreover, based on the growing increase in the dynamic environment and the heterogeneous nature of different applications and services to be supported by the systems, we discuss the reconfigurable and sliceable TRxs that can be employed. The associated technical challenges of various system algorithms are reviewed, and we proffer viable solutions to address them.

Performance Analysis of Adiabatic Vedic Multipliers

Energy dissipation and reliability are the two important design constraints in the high performance processor design. With the advancements in the IC manufacturing and reduced feature sizes the energy dissipation increases in exponential manner at the lower technology nodes. So, there is a need to design energy-efficient and reliable circuits and systems. The reliability with temperature is also one of the major challenges in today’s smart systems as they are operated in harsh environments. Most of the works till date analyzed the reliability with respect to DC constraints. The basic operation in the high performance Digital Signal Processing (DSP) is the multiplication is used to simplify various operations like convolution, filtering and correlation. In this work, a Vedic multiplier with 4x4 size is implemented with FinFET based energy recovery Modified PFAL (MPFAL) logic at 45 nm technology node. The designed multiplier performance is analyzed and compared with our earlier work in terms of energy dissipation and delay. The results indicate a reduction of 55% in energy dissipation over ECRL based Vedic multiplier. Linear variation of power dissipation with temperature in the order of pW shows that design MPFAL Vedic muliplier is more reliable compared to CMOS multiplier.

Low Complexity DSP for High Speed Optical Access Networking

A novel low-cost and energy-efficient approach for reaching 40 Gb/s signals is proposed for cost-sensitive optical access networks. Our proposed design is constituted of an innovative low-complex high-performance digital signal processing (DSP) architecture for pulse amplitude modulation (PAM-4), reuses existing commercial cost-effective 10-G components and eliminates the need of a power-hungry radio frequency (RF) component in the transmitter. Using a multi-functional 17-tap reconfigurable adaptive Volterra-based nonlinear equalizer with noise suppression, significant improvement in receiver optical power sensitivity is achieved. Results show that over 30 km of single-mode fiber (SMF) a link power budget of 33 dB is feasible at a bit-error-rate (BER) threshold of 10−3.

Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks

The advent of space applications with increased computational requirements has led the space industry to consider innovative chips and avionics architectures for high-performance on-board data processing. In a relatively limited market, the European BRAVE family of Field-Programmable Gate Arrays (FPGAs) offers such novel radiation-hardened solutions. Towards verification, the current work devises and applies a methodology to thoroughly assess the BRAVE FPGAs and their SW tools. The paper focuses on NG-Large, i.e., the largest FPGA of the 65nm Radiation-Hardened-By-Design (RHBD) technology of NanoXplore to date. The proposed approach comprises a number of customized steps to systematically evaluate the entire FPGA design flow. Initially, we carefully select and tune a set of high-performance Digital Signal Processing (DSP) & Computer Vision (CV) benchmarks, which were originally developed as Hardware Description Language (HDL) IPs in past projects of the European Space Agency (ESA). Subsequently, we perform exhaustive exploration of the Synthesis, Placement, and Routing stages of the SW tools, as well as testing on actual HW boards. At each step, we generate and analyze a variety of results, while we also compare them to 3rd-party solutions. The results show that NG-Large provides sufficient programmability and performance, e.g., classic CV IPs for feature detection on megapixel images can achieve a throughput of 5–10 frames per second, while the on-chip memory utilization is up to 56% better than that of 3rd-party FPGAs. As a highlight, at system-level, we successfully implement and execute an entire HW/SW algorithmic pipeline for Vision-Based Navigation (VBN) involving SpaceWire data transfers with LEON CPU & NG-Large co-processing.

200 Gbps/Lane IM/DD Technologies for Short Reach Optical Interconnects

Client-side optics are facing an ever-increasing upgrading pace, driven by upcoming 5G related services and datacenter applications. The demand for a single lane data rate is soon approaching 200 Gbps. To meet such high-speed requirement, all segments of traditional intensity modulation direct detection (IM/DD) technologies are being challenged. The characteristics of electrical and optoelectronic components and the performance of modulation, coding, and digital signal processing (DSP) techniques are being stretched to their limits. In this context, we witnessed technological breakthroughs in several aspects, including development of broadband devices, novel modulation formats and coding, and high-performance DSP algorithms for the past few years. A great momentum has been accumulated to overcome the aforementioned challenges. In this article, we focus on IM/DD transmissions, and provide an overview of recent research and development efforts on key enabling technologies for 200 Gbps per lane and beyond. Our recent demonstrations of 200 Gbps short-reach transmissions with 4-level pulse amplitude modulation (PAM) and discrete multitone signals are also presented as examples to show the system requirements in terms of device characteristics and DSP performance. Apart from digital coherent technologies and advanced direct detection systems, such as Stokes–vector and Kramers–Kronig schemes, we expect high-speed IM/DD systems will remain advantageous in terms of system cost, power consumption, and footprint for short reach applications in the short- to mid- term perspective.

Online Autotuning Technique for IPMSM Servo Drive by Intelligent Identification of Moment of Inertia

In this article, a real-time moment of inertia identification technique using Petri probabilistic fuzzy neural network with an asymmetric membership function (PPFNN-AMF) for an interior permanent magnet synchronous motor (IPMSM) servo drive is proposed. The estimated moment of inertia will be used in the online design of an integral–proportional (IP) speed controller to achieve the gains autotuning of the IPMSM servo drive. In the proposed method, the dynamic analysis of a field-oriented control IPMSM servo drive system with an IP speed controller is constructed first. Then, a heuristic approach using the PPFNN-AMF is proposed for the real-time identification of the moment of inertia of the IPMSM servo drive system. Moreover, the network structure and the convergence analysis of the PPFNN-AMF are devised and derivated. Furthermore, an IPMSM servo drive based on a high-performance digital signal processor is developed. Finally, from the experimental results, the gains of the IP speed controller can be tuned online effectively at different operating conditions with robust control characteristics.

Comparative performance analysis of FPGA-based MAC unit using non-conventional number system in TVL domain for signal processing algorithm

Today, the complication of binary digital hardware system is progressively growing. Due to this fact, new methodologies for efficiently describing and realising the digital systems are explored in this paper. Multi-valued logic methodology offers a few preferences over existing binary digital system. One of the well-known multi-valued logic systems is ternary value logic (TVL) system. It is seen that all kind of digital signal processing (DSP) algorithms widely use multiply-accumulate (MAC) operation for superior digital processing system. To implement high performance DSP algorithms MAC unit is used extensively. In current scenario, it is seen that non-conventional, non-binary number system-based architecture is also exhibited better performance. The example of such non-conventional, non-binary number systems is ternary residue number systems (TRNSs) and double base ternary number system (DBTNS). Here, a comparative study is made on performance analysis of MAC unit using various non-conventional, non-binary number system. All the architecture is mapped on FPGA for analysis its performance.

Comparative performance analysis of FPGA-based MAC unit using non-conventional number system in TVL domain for signal processing algorithm

Today, the complication of binary digital hardware system is progressively growing. Due to this fact, new methodologies for efficiently describing and realising the digital systems are explored in this paper. Multi-valued logic methodology offers a few preferences over existing binary digital system. One of the well-known multi-valued logic systems is ternary value logic (TVL) system. It is seen that all kind of digital signal processing (DSP) algorithms widely use multiply-accumulate (MAC) operation for superior digital processing system. To implement high performance DSP algorithms MAC unit is used extensively. In current scenario, it is seen that non-conventional, non-binary number system-based architecture is also exhibited better performance. The example of such non-conventional, non-binary number systems is ternary residue number systems (TRNSs) and double base ternary number system (DBTNS). Here, a comparative study is made on performance analysis of MAC unit using various non-conventional, non-binary number system. All the architecture is mapped on FPGA for analysis its performance.

Background free imaging in stimulated emission fluorescence microscopy

Recently, the pump-probe technique has found highly valued developments and applications in optical microscopy to study both labeled (fluorescence) and non-labeled (vibrational) for observation of cells and tissues. In this work, we use the mechanism of stimulated emission (SE) with dual frequency modulation to remove the large background signal that is originated from spontaneous emission. We have applied a high performance digital signal processing based lock-in detection for stimulated emission fluorescence microscopy. Critically, the pump beam is modulated at f1 and the probe beam is at a different frequency, f2, with the demodulation carried out at the sum of the two frequencies, (f1 + f2). In this way, the DC background is effectively removed. Note that the background is mainly attributed to the spontaneous emission of the pump beam, with modulated frequency f1.

High‐performance DSP platform for digital hearing aid SoC with flexible noise estimation

Flexibility and programmability of hearing aids are important because the algorithms applied to hearing aids should be changeable based on different types of hearing impairment and the ambient environment of the user. This paper proposes a high-performance digital signal processing (DSP) platform for a digital hearing aid system on a chip (SoC) with flexible noise estimation. The proposed DSP platform comprises several dedicated accelerators and an application-specific instruction-set processor (ASIP) to achieve flexibility. To handle complex hearing aid algorithms in real time, the main algorithms of hearing aids are executed by hardware accelerators and only environment-sensitive parts of the applied algorithms are implemented as the ASIP. Simulation results show that the proposed DSP platform can handle complex and high-performance algorithms in real time, and that it provides better quality in terms of noise handling by adapting the noise estimation algorithms suitable for the noise environment. The chip area of authors’ DSP design is 2.71 mm2, and it consumes 1.3 mW at 1 V operation, 8 MHz clock frequency with a 65 nm high threshold voltage (HVT) standard cell library.

Loop Parallelism Maximization for Multimedia Data Processing in Mobile Vehicular Clouds

Mobile vehicular cloud has become popular with the rapid development of cloud computing and mobile computing. Nested loops are usually the most critical part in multimedia and high performance Digital Signal Processing (DSP) systems which are widely used in vehicular applications and systems. In order to further explore the parallelism in nested loops, we study how to maximize the system performance with considering the energy reduction for applications on Chip Multiprocessor (CMP) architectures. We propose an algorithm Energy-Aware Loop Parallelism Maximization (EALPM) to maximize the system performance with the consideration of energy reduction for applications with multidimensional nested loops. Our experiment shows that using the EALPM algorithm significantly improves both performance and energy consumption on average in comparision to other algorithms.

Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery

Approximate circuits have been considered for applications that can tolerate some loss of accuracy with improved performance and/or energy efficiency. Multipliers are key arithmetic circuits in many of these applications including digital signal processing (DSP). In this paper, a novel approximate multiplier with a low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbors for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery circuit. The approximate multipliers using these two error reduction strategies are referred to as AM1 and AM2, respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Wallace multiplier optimized for speed, an $8\times 8$ AM1 using four most significant bits for error reduction shows a 60% reduction in delay (when optimized for delay) and a 42% reduction in power dissipation (when optimized for area). In a $16\times 16$ design, half of the least significant partial products are truncated for AM1 and AM2, which are thus denoted as TAM1 and TAM2, respectively. Compared with the Wallace multiplier, TAM1 and TAM2 save from 50% to 66% in power, when optimized for area. Compared with existing approximate multipliers, AM1, AM2, TAM1, and TAM2 show significant advantages in accuracy with a low power-delay product. AM2 has a better accuracy compared with AM1 but with a longer delay and higher power consumption. Image processing applications, including image sharpening and smoothing, are considered to show the quality of the approximate multipliers in error-tolerant applications. By utilizing an appropriate error recovery scheme, the proposed approximate multipliers achieve similar processing accuracy as exact multipliers, but with significant improvements in power.

Design and Application Space Exploration of a Domain-Specific Accelerator System

Domain-specific accelerators are a reaction adapting to device scaling and the dark silicon era. This paper describes a radar signal processing oriented configurable accelerator and the application space exploration of the system. The system is built around accelerator engines and general-purpose processors (GPPs) that make it suitable for intensive computing kernel acceleration and complex control tasks. It is geared toward high-performance radar digital signal processing; we characterize the applications and find that each of them contains a series of serializable kernels. Taking advantage of this discovery, we design an algorithm pool that shares the same computation resource and memory resource, and each algorithm is size reconfigurable. On the other hand, shared on-chip addressable scratchpad memory eliminates unnecessary explicit data copy between accelerators. Performance of the system is evaluated from measurements performed both on an FPGA SoC test chip and on a prototype chip fabricated by CMOS 40 nm technology. The experimental results show that for different algorithms, the proposed system achieves 1.9× to 10.1× performance gain compared with a state-of-the-art TI DSP chip. In order to characterize the application of the system, a complex real-life task is adopted, and the results show that it can obtain high throughput and desirable precision.

Design and Implementation of Power Efficient Modified Russian Peasant Multiplier using Ripple Carry Adder

FIR filters, microprocessor and digital signal processor are the core system of multipliers. MAC is the most important building block in DSP system. The key element of high throughput multiplier and accumulator unit (MAC) is to achieve a high-performance digital signal processing application. In this paper, Modified Russian Peasant Multiplier (MRPM) using Ripple Carry Adder (RCA) has been proposed. According to Russian Rule‟s, Divide and conquer technique is used in the multiplication process. But, in perspective of digital design, only shifters and adders are used in Russian Peasant Multiplier to produce Partial Product Generation (PPG). A ripple carry adder is a logic circuit in which the carry-out of each full adder is the carry in of the next most significant full adder. It is called a ripple carry adder because each carry bit gets rippled into the next stage. Here, ripple carry adder is used for low power application. Reducing the chip size, increasing the speed and reducing the power consumption are main crucial factors in VLSI System design environment. The goal of this research work is to design the VLSI implementation of MAC for high-speed DSP applications. For designing the Multiplication and accumulation unit, different kinds of multipliers and adders are considered in this paper. The total operation is coded with Verilog HDL using ModelSim 6.3C, synthesized by using Xilinx ISE 12.4i design tool.