High Performance Computing Applications Research Articles

Simplifying the Development, Use and Sustainability of HPC Software

Developing software to undertake complex, compute-intensive scientific processes requires a challenging combination of both specialist domain knowledge and software development skills to convert this knowledge into efficient code. As computational platforms become increasingly heterogeneous and newer types of platform such as Infrastructure-as-a-Service (IaaS) cloud computing become more widely accepted for high-performance computing (HPC), scientists require more support from computer scientists and resource providers to develop efficient code that offers long-term sustainability and makes optimal use of the resources available to them. As part of the libhpc stage 1 and 2 projects we are developing a framework to provide a richer means of job specification and efficient execution of complex scientific software on heterogeneous infrastructure. In this updated version of our submission to the WSSSPE13 workshop at SuperComputing 2013 we set out our approach to simplifying access to HPC applications and resources for end-users through the use of flexible and interchangeable software components and associated high-level functional-style operations. We believe this approach can support sustainability of scientific software and help to widen access to it.

Performance and power consumption evaluation of concurrent queue implementations in embedded systems

Embedded and high performance computing (HPC) systems face many common challenges. One of them is the synchronization of the memory accesses in shared data. Concurrent queues have been extensively studied in the HPC domain and they are used in a wide variety of HPC applications. In this work, we evaluate a set of concurrent queue implementations in an embedded platform, in terms of execution time and power consumption. Our results show that by taking advantage of the embedded platform specifications, we achieve up to 28.2 % lower execution time and 6.8 % less power dissipation in comparison with the conventional lock-based queue implementation. We show that HPC applications utilizing concurrent queues can be efficiently implemented in embedded systems and that synchronization algorithms from the HPC domain can lead to optimal resource utilization of embedded platforms.

Simulation and optimization of HPC job allocation for jointly reducing communication and cooling costs

Performance and energy are critical aspects in high performance computing (HPC) data centers. Highly parallel HPC applications that require multiple nodes usually run for long durations in the range of minutes, hours or days. As the threads of parallel applications communicate with each other intensively, the communication cost of these applications has a significant impact on data center performance. Energy consumption has also become a first-order constraint of HPC data centers. Nearly half of the energy in the computing clusters today is consumed by the cooling infrastructure. Existing job allocation policies either target improving the system performance or reducing the cooling energy cost of the server nodes. How to optimize the system performance while minimizing the cooling energy consumption is still an open question. This paper proposes a job allocation methodology aimed at jointly reducing the communication cost and the cooling energy of HPC data centers. In order to evaluate and validate our optimization algorithm, we implement our joint job allocation methodology in the structural simulation toolkit (SST) – a simulation framework for large-scale data centers. We evaluate our joint optimization algorithm using traces extracted from real-world workloads. Experimental results show that, in comparison to performance-aware job allocation algorithms, our algorithm achieves comparable running times and reduces the cooling power by up to 42.21% across all the jobs.

Xen2MX: High-performance communication in virtualized environments

Cloud computing infrastructures provide vast processing power and host a diverse set of computing workloads, ranging from service-oriented deployments to high-performance computing (HPC) applications. As HPC applications scale to a large number of VMs, providing near-native network I/O performance to each peer VM is an important challenge. In this paper we present Xen2MX, a paravirtual interconnection framework over generic Ethernet, binary compatible with Myrinet/MX and wire compatible with MXoE. Xen2MX combines the zero-copy characteristics of Open-MX with Xen's memory sharing techniques. Experimental evaluation of our prototype implementation shows that Xen2MX is able to achieve nearly the same raw performance as Open-MX running in a non-virtualized environment. On the latency front, Xen2MX performs as close as 96% to the case where virtualization layers are not present. Regarding throughput, Xen2MX saturates a 10Gbps link, achieving 1159MB/s, compared to 1192MB/s of the non-virtualized case. Scales efficiently with the number of VMs, saturating the link for even smaller messages when 40 single-core VMs put pressure on the network adapters.

A HPC based cloud model for real-time energy optimisation

Recent research has emphasised that an increasing number of enterprises need computation environments for executing HPC (High Performance Computing) applications. Rather than paying the cost of ownership and possess physical, fixed capacity clusters, enterprises can reserve or rent resources for undertaking the required tasks. With the emergence of new computation paradigms such as cloud computing it has become possible to solve a wider range of problems due to their capability to handle and process massive amounts of data. On the other hand, given the pressing regulatory requirement to reduce the carbon footprint of our built environment, significant researching efforts have been recently directed towards simulation-based building energy optimisation with the overall objective of reducing energy consumption. Energy optimisation in buildings represents a class of problems that requires significant computation resources and generally is a time consuming process especially when undertaken with building simulation software, such as EnergyPlus. In this paper we present how a HPC based cloud model can be efficiently used for running and deploying EnergyPlus simulation-based optimisation in order to fulfil a number of objectives related to energy consumption. We describe and evaluate the establishment of such an application-based environment, and consider a cost perspective to determine the efficiency over several cases we explore. This study identifies the following contributions: (i) a comprehensive examination of issues relevant to the HPC community, including performance, cost, user perspectives and range of user activities, (ii) a comparison of two different execution environments such as HTCondor and CometCloud and determine their effectiveness in supporting simulation-based optimisation and (iii) a detailed performance analysis to locate the limiting factors of these execution environments.

Self-service for software development projects and HPC activities

This contribution describes how CERN has implemented several essential tools for agile software development processes, ranging from version control (Git) to issue tracking (Jira) and documentation (Wikis). Running such services in a large organisation like CERN requires many administrative actions both by users and service providers, such as creating software projects, managing access rights, users and groups, and performing tool-specific customisation. Dealing with these requests manually would be a time-consuming task. Another area of our CERN computing services that has required dedicated manual support has been clusters for specific user communities with special needs. Our aim is to move all our services to a layered approach, with server infrastructure running on the internal cloud computing infrastructure at CERN. This contribution illustrates how we plan to optimise the management of our of services by means of an end-user facing platform acting as a portal into all the related services for software projects, inspired by popular portals for open-source developments such as Sourceforge, GitHub and others. Furthermore, the contribution will discuss recent activities with tests and evaluations of High Performance Computing (HPC) applications on different hardware and software stacks, and plans to offer a dynamically scalable HPC service at CERN, based on affordable hardware.

Heterogeneous Integration of Plasmonics with Si-Photonics & Microelectronics for High-Performance Optical Routing

Advanced packaging technologies impact future systems, since packaging determines functionality, cost and reliability of future systems. The future systems are very high complex systems and contain different physical functions. Therefore modularity in heterogeneous integration is required. Future systems combine optical and ultra high frequency functions. With this a large variety of materials will be applied. For all these components a common smart support substrate such as ‘Silicon’ will be of importance for future systems. Furthermore, System-in-Package is must for future subsystems in order to overcome the challenges.In tems of of today’s Peta-flop High-Performance Computing (HPC) applications the size and power consumption appear to be critical issues, signifying that new technological and architectural considerations are required in order to be able to move towards Exascale-computing powers. Whereas silicon photonics emerges as a powerful technology for low-loss and high bandwidth optical connectivity in integrated circuit environments, servers and network switches are already consolidating into high-density blade enclosures in order to reduce space and cooling requirements. These considerations determine additional tasks for switching infrastructures of miniature data networks: the next generation of routing circuitry has to provide high throughput capabilities while keeping in line with the requirements of small foot-print, low power consumption and low latency. Here, next generation computing architectures are needed with ultra low power consumption; ultra high performance with novel photonic interconnection technologies. The objective of the recently proposed high bandwidth photonics interconnection layer for converged microsystems using System-in-Package Technology, is to develop a CMOS compatible underlying technology to enable next generation optical computing architectures.We present within the framework of EU-PLATON project a photonic integrated system-in-package platform for Tb/s optical routing, where three different technologies, silicon photonics, plasmonics and electronics are merged. Compatibility between various components has to be ensured to allow for their seamless interfacing and interoperability. The 4x4 router architecture exploits a SOI platform employing 340x400nm2 waveguide structures and hosting four 7:1 SOI multiplexing circuits, four photodiodes, an electronic IC control circuit and the 4x4 dielectric-loaded surface plasmon-polariton (DLSPP)-based switching matrix.This work has been partly supported by the European FP7 research program PLATON, Contract Number 249135. www.ict-platon.eu

Implementation and verification of the Park–Paulino–Roesler cohesive zone model in 3D

The Park–Paulino–Roesler (PPR) potential-based model is a cohesive constitutive model formulated to be consistent under a high degree of mode-mixity. Herein, the PPR’s generalization to three-dimensions is detailed, its implementation in a finite element framework is discussed, and its use in single-core and high performance computing (HPC) applications is demonstrated. The PPR model is shown to be an effective constitutive model to account for crack nucleation and propagation in a variety of applications including adhesives, composites, linepipe steel, and microstructures.

FastMPJ: a scalable and efficient Java message-passing library

The performance and scalability of communications are key for high performance computing (HPC) applications in the current multi-core era. Despite the significant benefits (e.g., productivity, portability, multithreading) of Java for parallel programming, its poor communications support has hindered its adoption in the HPC community. This paper presents FastMPJ, an efficient message-passing in Java (MPJ) library, boosting Java for HPC by: (1) providing high-performance shared memory communications using Java threads; (2) taking full advantage of high-speed cluster networks (e.g., InfiniBand) to provide low-latency and high bandwidth communications; (3) including a scalable collective library with topology aware primitives, automatically selected at runtime; (4) avoiding Java data buffering overheads through zero-copy protocols; and (5) implementing the most widely extended MPI-like Java bindings for a highly productive development. The comprehensive performance evaluation on representative testbeds (InfiniBand, 10 Gigabit Ethernet, Myrinet, and shared memory systems) has shown that FastMPJ communication primitives rival native MPI implementations, significantly improving the efficiency and scalability of Java HPC parallel applications.

Cost-oriented proactive fault tolerance approach to high performance computing (HPC) in the cloud

Cloud computing offers new computing paradigms, capacity and flexible solutions to high performance computing (HPC) applications. For example, Hardware as a Service (HaaS) allows users to provide a large number of virtual machines (VMs) for computation-intensive applications using the HaaS model. Due to the large number of VMs and electronic components in HPC system in the cloud, any fault during the execution would result in re-running the applications, which will cost time, money and energy. In this paper we presented a proactive fault tolerance (FT) approach to HPC systems in the cloud to reduce the wall-clock execution time and dollar cost in the presence of faults. We also developed a generic FT algorithm for HPC systems in the cloud. Our algorithm does not rely on a spare node prior to prediction of a failure. We also developed a cost model for executing computation-intensive applications on HPC systems in the cloud. We analysed the dollar cost of provisioning spare nodes and checkpointing FT to assess the value of our approach. Our experimental results obtained from a real cloud execution environment show that the wall-clock execution time and cost of running computation-intensive applications in cloud can be reduced by as much as 30%. The frequency of checkpointing of computation-intensive applications can be reduced up to 50% with our FT approach for HPC in the cloud compared with current FT approaches.

Improving HPC Application Performance in Public Cloud

Improving as well as evaluating the performance of High Performance Computing (HPC) applications by migrating them to Cloud environments are widely considered as critical issues in the field of high performance and Cloud computing. However, poor network performance, heterogeneous and dynamic environments are some series of pitfalls for execution of HPC applications in Cloud. This paper proposes a new approach to improve the performance and scalability of HPC applications on Amazon's HPC Cloud. The evidence from our approach points a significant improvement in speed up and scale up with the response rate of more than 20 percent parallel efficiency on the Cloud in comparison to dedicated HPC cluster. We state that the EC2 Cloud system is a feasible platform for deploying on-demand, small sized HPC applications.

Coordinated Energy Management in Heterogeneous Processors

This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC) applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2) product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.

Coordinated Energy Management in Heterogeneous Processors

This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC) applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2) product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.

ADVANCED ORGANIC SUBSTRATE TECHNOLOGIES FOR HIGH PERFORMANCE, HIGH RELIABILITY ELECTRONICS MINIATURIZATION

High reliability applications for high performance computing, military, medical and industrial applications are driving electronics packaging advancements toward increased functionality with decreasing degrees of size, weight and power (SWaP) The substrate technology selected for the electronics package is a key enabling technology towards achieving SWaP. Standard printed circuit boards (PWBs) utilize dielectric materials containing glass cloth, which can limit circuit density and performance, as well as inhibit the ability to achieve reliable assemblies with bare semiconductor die components. Ceramic substrates often used in lieu of PWBs for chip packaging have disadvantages of weight, marginal electrical performance and reliability as compared to organic technologies. Alternative materials including thin, particle-containing organic substrates, liquid crystal polymer (LCP) and microflex enable SWaP, while overcoming the limitations of PWBs and ceramic. This paper will discuss the use of these alternative organic substrate materials to achieve extreme electronics miniaturization with outstanding electrical performance and high reliability. The effect of substrate type on chip-package interaction and resulting reliability will be discussed in detail, and compared to standard PWB and ceramic. Microflex assemblies to achieve extreme miniaturization and atypical form factors driven by implantable and in vivo medical applications are also shown.

A High Performance Computing Platform for Performing High-Volume Studies with Windows-based Power Grid Tools

Serial Windows-based programs are widely used in power utilities. For applications that require high-volume simulations, the sequential runtime can be in the order of days or weeks. The lengthy runtime, along with the availability of low-cost hardware, is leading utilities to seriously consider high performance computing (HPC) techniques. However, the majority of the HPC computers are Linux-based, and many HPC applications have been custom developed without considering existing simulation tools and ease of use. This has created a technical gap for applying HPC-based tools to today's power grid studies using Windows-based tools. To fill this gap and accelerate the acceptance and adoption of HPC for power grid applications, this paper presents a prototype of a generic HPC platform for running Windows-based power grid tools on the Linux-based HPC environment. The preliminary results show that the runtime can be significantly reduced from weeks to hours to improve work efficiency.

Exploring the Future of Out-of-Core Computing with Compute-Local Non-Volatile Memory

Drawing parallels to the rise of general purpose graphical processing units (GPGPUs) as accelerators for specific high-performance computing (HPC) workloads, there is a rise in the use of non-volatile memory (NVM) as accelerators for I/O-intensive scientific applications. However, existing works have explored use of NVM within dedicated I/O nodes, which are distant from the compute nodes that actually need such acceleration. As NVM bandwidth begins to out-pace point-to-point network capacity, we argue for the need to break from the archetype of completely separated storage. Therefore, in this work we investigate co-location of NVM and compute by varying I/O interfaces, file systems, types of NVM, and both current and future SSD architectures, uncovering numerous bottlenecks implicit in these various levels in the I/O stack. We present novel hardware and software solutions, including the new Unified File System (UFS), to enable fuller utilization of the new compute-local NVM storage. Our experimental evaluation, which employs a real-world Out-of-Core (OoC) HPC application, demonstrates throughput increases in excess of an order of magnitude over current approaches.

Exploring the Future of Out-of-Core Computing with Compute-Local Non-Volatile Memory

Drawing parallels to the rise of general purpose graphical processing units (GPGPUs) as accelerators for specific high-performance computing (HPC) workloads, there is a rise in the use of non-volatile memory (NVM) as accelerators for I/O-intensive scientific applications. However, existing works have explored use of NVM within dedicated I/O nodes, which are distant from the compute nodes that actually need such acceleration. As NVM bandwidth begins to out-pace point-to-point network capacity, we argue for the need to break from the archetype of completely separated storage. Therefore, in this work we investigate co-location of NVM and compute by varying I/O interfaces, file systems, types of NVM, and both current and future SSD architectures, uncovering numerous bottlenecks implicit in these various levels in the I/O stack. We present novel hardware and software solutions, including the new Unified File System (UFS), to enable fuller utilization of the new compute-local NVM storage. Our experimental evaluation, which employs a real-world Out-of-Core (OoC) HPC application, demonstrates throughput increases in excess of an order of magnitude over current approaches.

Performance Optimization for Sparse <i>A<sup>t</sup>Ax</i> in Parallel on Multicore CPU

The sparse matrix operation, y ← y+AtAx, where A is a sparse matrix and x and y are dense vectors, is a widely used computing pattern in High Performance Computing (HPC) applications. The pattern poses challenge to efficient solutions because both a matrix and its transposed version are involved. An efficient sparse matrix format, Compressed Sparse Blocks (CSB), has been proposed to provide nearly the same performance for both Ax and Atx. We develop a multithreaded implementation for the CSB format and apply it to solve y ← y+AtAx. Experiments show that our technique outperforms the Compressed Sparse Row (CSR) based solution in POSKI by up to 2.5 fold on over 70% of benchmarking matrices.

A review of High Performance Computing

Current high performance computing (HPC) applications are found in many consumers, industrial and research fields. There is a great deal more to remote sensing data than meets the eye, and extracting that information turns out to be a major computational challenges, so the high performance computing (HPC) infrastructure such as MPP (massive parallel processing), clusters, distributed networks or specialized hardware devices are used to provide important architectural developments to accelerate the computations related with information extraction in remote sensing. The focus of HPC has shifted towards enabling the transparent and most efficient utilization of a wide range of capabilities made available over networks. In this paper we review the fundamentals of High Performance Computing (HPC) in a way which is easy to understand and sketch the way to standard computers and supercomputers work, as well as discuss distributed computing and essential aspects to take into account when running scientific calculations in computers.

Performance Improvements for a Large-scale Geological Simulation

Geological models have been successfully used to identify and study geothermal energy resources. Many computer simulations based on these models are data-intensive applications. Large-scale geological simulations require high performance computing (HPC) techniques to run within reasonable time constraints and performance levels. One research area that can benefit greatly from HPC techniques is the modeling of heat flow beneath the Earth's surface. This paper describes the application of HPC techniques to increase the scale of research with a well-established geological model. Recently, a serial C++ application based on this geological model was ported to a parallel HPC applications using MPI. An area of focus was to increase the performance of the MPI version to enable state or regional scale simulations using large numbers of processors. First, synchronous communications among MPI processes was replaced by overlapping communication and computation (asynchronous communication). Asynchronous communication improved performance over synchronous communications by averages of 28% using 56 cores in one environment and 46% using 56 cores in another. Second, an approach for load balancing involving repartitioning the data at the start of the program resulted in runtime performance improvements of 32% using 48 cores in the first environment and 14% using 24 cores in the second when compared to the asynchronous version. An additional feature, modeling of erosion, was also added to the MPI code base. The performance improvement techniques under erosion were less effective.