High-performance Circuit Design Research Articles

Unveiling the mechanism behind the negative capacitance effect in Hf0.5Zr0.5O2-Based ferroelectric gate stacks and introducing a Circuit-Compatible hybrid compact model for Leakage-Aware NCFETs

This paper addresses the lack of understanding of the origin of negative capacitance (NC) effect in the hafnium zirconium oxide (HZO) ferroelectric (FE) gate stack and proposes a new circuit-compatible hybrid compact model for NC field-effect transistors (NCFETs). The model supports Landau and Preisach FE models, encompassing multiple FE domains, FE leakage, and FE damping. The proposed model is experimentally validated, and the intrinsic switching speed of HZO is predicted. It is revealed that the NC effect in HZO stems from a mismatch in free charge and polarization switching rates. Performance evaluation of the model reveals that HZO-NCFET achieves ∼1.18x and ∼9.17x higher amplification at low and high frequencies compared to its PZT-NCFET counterpart. Our study demonstrates the superior ON-current (2.74 mA/µm) of the Engineered Leaky-HZO NCFET, surpassing FinFET and Germanium-source L-shaped TFET by ∼7.89x and ∼4.81x, respectively. This study briefly examines the direct causes of the negative drain-induced barrier lowering effect and negative differential resistance effect in Landau NCFETs. Furthermore, we emphasize the crucial role of FE thickness in determining the magnitude of the NC effect, offering valuable insights for the design and optimization of NC-based devices and circuits. Analysis of the Miller effect in NCFET-based inverters demonstrates significant improvements owing to high ON-current and voltage amplification, making them suitable for high-speed NCFET-based circuitry. Landau and Preisach NCFET-based inverters exhibit (50.70%, 51.34%) lower overshoots and (28.45%, 28.61%) reduced propagation delay compared to the NC nanowire FET-based inverter. Moreover, NCFET-based 2:1 fork circuits significantly reduce (46.69%, 51.37%) critical clock skew compared to CMOS FET-based circuits, showcasing the potential of NCFET technology in addressing timing violations in random logic paths. Furthermore, the Landau and Preisach NCFET-based ring oscillators (ROs) achieve (39.97%, 49.38%) and (52.65%, 62.92%) higher oscillation frequencies (fOSC) compared to state-of-the-art graphene FET-RO and CMOS-RO, respectively. The 15-stage Leaky-HZO and Engineered Leaky-HZO NCFET-ROs outperform the double gate-FET-RO by ∼2.19x and ∼16.69x in terms of fOSC, highlighting their superior performance in frequency-domain metrics. These findings demonstrate the potential of NCFET-based digital and mixed-signal circuits for high-performance integrated circuit designs.

High-performance LFSR circuit design based on XOR gates

The research discussed in this article is focused on analysing the effects of XOR gates based on different logic families, namely MOS Current Mode Logic (MCML), dynamic current logic, and PTL, on the performance of linear feedback shift register (LFSR) circuits. The aim of the study is to evaluate the power dissipation and critical path latency of the circuits while comparing the results with earlier works in the field. To achieve this, the researchers implemented the 3, 4, and 5-bit LFSR circuits using Verilog HDL code and synthesized them on the Cadence tool using 90nm CMOS technology. The study concludes that LFSR circuits based on XOR gates outperform previous LFSR circuits in terms of power dissipation. The research also offers a comparative analysis of the different types of XOR gates used in the LFSR circuits, highlighting the advantages and disadvantages of each type. The results of the study can be useful for researchers working in the field of circuit design, as well as for practitioners who are interested in developing low-power and efficient LFSR circuits.

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

The GAA FET has emerged as a promising device due to its excellent control over short-channel effects and improved electrostatic control. This manuscript presents the analytical modelling for the Dual Material Graded Channel (DMGC) Cylindrical GAA FET to characterize the drain current in linear, saturation, as well as subthreshold regions. The model incorporates the effect of supply voltage, radius, and thickness of oxide layer on the device enabling a comprehensive analysis of the device behaviour. The influence of subthreshold swing is also presented. Next, the analysis is extended to investigate the important analog performance parameters that includes transconductance and output conductance. The validation of the analytical model across a wide range of operating conditions with the simulated data is performed and observed to be a close match. Building upon the insights gained from the analytical modelling, a common source amplifier based on the DMGC CGAA FET is designed. The amplifier’s performance has been optimized by carefully selecting the biasing conditions and a maximum gain value of 7.745 is achieved. Further, an improvement of 42.28% in output voltage is observed for DMGC in comparison with SMGC making it a promising device for high-performance integrated circuit design.

SYSTEM ANALYSIS OF MAINTENANCE OF THE ELECTRICAL COMPLEX

Modern electronic devices are characterized by complex circuit design solutions, which requires performing their design using high-performance circuit design computer-aided design systems. The development of such computer-aided design systems is associated with significant expenditure of time and labor resources and should be based on new approaches to the construction of mathematical and software, taking into account the specific features of the subject area and the nature of the tasks to be solved. In this paper, the problems associated with the modeling of maintenance of electrical complex are considered. A methodology for predicting components based on a single attribute within an experiment is demonstrated. The criterion in terms of risk assessment for the consumer is considered. The results of modeling the main parameters characterizing the quality of electrolytic capacitors are presented. After the tests are completed, the value of the predicted parameter is determined for each realization. The optimum value of leakage current, providing the minimum probability of error, for tantalum electrolytic capacitors with nominal capacity is shown. The results of the research can be useful for specialists working on electrical engineering complexes.

IEEE SSCS Leuven Student Chapter Hosts Distinguished Lecturer Prof. Tony Tae-Hyoung Kim From NTU in Singapore [Chapters

On 21 November 2022, the IEEE Solid-State Circuits Society (SSCS) Leuven Student Chapter hosted a technical talk given by Prof. Tony Tae-Hyoung Kim at KU Leuven, Belgium. Kim received his M.S. degree from Korea University in Seoul, South Korea, and his Ph.D. degree from the University of Minnesota in Minneapolis. He is currently an associate professor at Nanyang Technological University (NTU) in Singapore and mainly performs research in the field of computing in memory (CIM) and low-power and high-performance digital, mixed-mode, and memory circuit design. In 2022–2023, he was elected as a distinguished lecturer for the SSCS.

Importance of Leakage Magnetic Field and Fringing Flux in Surge Protector Design

Transient surge absorption capability of supercapacitors is practically implemented in a commercial surge protector known as supercapacitor assisted surge absorber (SCASA). It is a low component count high performance circuit design which utilizes a coupled inductor topology wound to a powdered-iron magnetic core. This paper investigates non-ideal characteristics of the SCASA transformer designed using various air-gapped ferrites such as manually gapped toroids and mass-produced commercially available EER cores. Emphasis is given to examine surge energy losses associated with leakage magnetic field and fringing flux of gapped transformer prototypes. In predicting effects of an air gap in ferrite materials, an analytical approach based on effective-permeance is used with validations based on SCASA inductance properties. Experimental work presented in this paper are carried out using a Noiseken lightning surge simulator adhering to IEC 60038 and IEEE C62.41 standards. In addition, SCASA prototypes were subjected to surge immunity tests specified by UL-1449 Underwriters' laboratory procedures, where a 10% reduction of load-voltage was recorded outperforming the present design.

DESIGN OF LOW POWER HIGH SPEED CNTFET ADDER SUBTRACTOR

Multi-valued logic design itself is not sufficient to achieve the performance improvement in digital system design in nanotechnology. The need to replace silicon devices with some more efficient new devices are required so as to meet the power improvements in the nanoscale region. Among various devices explored, CNTFET is the most promising alternative to replace conventional MOS transistors. These nano devices have the benefits of low power consumption due to reduced leakage component, ballistic transport operation even at low supply voltages makes them suitable for high frequency and low voltage applications. MVL circuitry has soared in popularity because the threshold voltage of the CNFET device is somewhat adjustable by the diameter of carbon nanotubes. CNFET is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Carbon Nanotube Filed-Effect Transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometry- dependent threshold voltage is one of the CNFET characteristics, which is used in the proposed design. In this paper, we present a novel high speed Adder-subtractor cell using CNFETs based on XOR gates and multiplexer. Proposed design uses fourteen transistors, ten for full adder and four to modify the cell for subtraction. Simulation results show significant improvement in terms of delay and area saving with respectively compared to the latest design. Simulations were carried out using HSPICE based on CNFET model with optimized design parameters. All designs are simulated at 32nm CNFET with HSPICE. The simulation results show that on average, speed enhancement and area saving of 48% and 11% can be achieved with optimized parameters design over default values of these parameters. The cumulative benefits of the novel adder-subtractor design based CNFET result in an PDP reduction by a factor of 41%.

Design of a new multiplexer structure based on a new fault-tolerant majority gate in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology is believed to be a good alternative to CMOS technology. This nanoscale technology can provide a platform for design and implementation of high performance and power efficient logic circuits. However, the fabrication of QCA circuits is susceptible to faults appearing in this form of missing cells, additional cells, rotated cells and displaced cells. Over the years, several solutions have been proposed to address these problems. This paper presents a new solution for improving the fault tolerance of three input majority gate. The proposed majority gate is then used to design 2-1 multiplexer and 4-1 multiplexer. The proposed designs are implemented in QCA Designer. Simulation results demonstrate significant improvements in terms of fault tolerance and area requirement. The proposed gate consists of 11 cells and requires an area of 0.0096 μm2. The proposed design has 100% tolerance to the fault of a single missing cell and 71.43% tolerance to the rotation of one cell. The proposed 2-1 multiplexer consists of 41 cells and requires an area of 0.066 μm2. This multiplexer has 95.24% tolerance to the fault of a single missing cell.

Design of a triple pocket multi-gate material TFET structure for low-power applications

In this paper we propose a triple-pocket multi-gate material TFET (TP-TFET) device structure for a low-power and high-performance circuit design. The proposed device structure integrates the good features of both the conventional MOSFET and tunnel FET. This is achieved through three doped pockets and dual work-function gate material on near the source–channel junction. In the proposed device, the ON state conduction mechanism is dominated by an over-the-barrier thermal diffusion of carriers, thereby offering a high-value drive current. On the other hand, the subthreshold conduction mechanism is dominated by the tunnelling of carriers, thereby incurring a very small leakage current and offering a small subthreshold slope. We use 2D TCAD device simulations for the analysis of the TP-TFET and its comparison with the existing pocketed-heterogate TFET (PHG-TFET). We observe that the proposed TFET offers the average subthreshold slope (SSavg) of 2.85 mV dec−1 and ON current of ∼230 µA µm−1 as compared to the existing PHG-TFET, which offers SSavg of 44.91 mV dec−1 and I ON = ∼62 µA µm−1. Further, some benchmark circuits are implemented using these devices. A ring oscillator designed using the TP-TFET shows approximately a 6× higher frequency as compared to that designed using the PHG-TFET. The power delay product of the NAND gate and NOR gate obtained using these devices differ by approximately 3× to 20× as the supply voltage is decreased from 1.0 to 0.5 V.

An Efficient Ultra-Low-Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices

This paper presents a novel ultra-low power yet high-performance device and circuit design paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs (GOTFETs) and Carbon Nanotube FETs (CNFETs). One of the distinguishing novelty reported in this work is the introduction of an innovative GOTFET device, which exhibits more than double the on-currents I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> and less than 1/10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> the off-currents I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> of equivalent, equally-sized mosfets at the same technology node. Most of the ternary logic designs reported earlier in the literature encode ternary bits into binary for combinational functionality and then use an Encoder to get back ternary output. Unlike the earlier designs, this paper presents a novel and significantly more efficient approach of directly designing ternary logical functions with Low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> Transistors (LVT) and High V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> Transistors (HVT) using CNFET and GOTFET technologies. The new approach simplifies the design and reduces the required transistor count & interconnects, thereby reducing the delays and power consumption. The proposed Ternary Half Adder (THA) circuit, designed using CMOS, enables a 52% reduction in transistor count compared to the conventional CMOS designs available in the literature. The THA implemented with CNFET exhibits 27 ps (87% lower delay than similar CMOS design and consumes 2.4 μW power (11% lower than CMOS). On the other hand, CGOT THA exhibits 101 ps (51% lower delay than similar CMOS design) and consumes merely 1.26 μW power (53% lower than CMOS, in ultra-low power regime). The overall decrease in the Power Delay Products (PDPs) are 88% and 77%, respectively, in the proposed CNFET and CGOT THA circuits compared to the CMOS THA.

A Compact and Robust Technique for the Modeling and Parameter Extraction of Carbon Nanotube Field Effect Transistors

Carbon nanotubes field-effect transistors (CNTFETs) have been recently studied with great interest due to the intriguing properties of the material that, in turn, lead to remarkable properties of the charge transport of the device channel. Downstream of the full-wave simulations, the construction of equivalent device models becomes the basic step for the advanced design of high-performance CNTFET-based nanoelectronics circuits and systems. In this contribution, we introduce a strategy for deriving a compact model for a CNTFET that is based on the full-wave simulation of the 3D geometry by using the finite element method, followed by the derivation of a compact circuit model and extraction of equivalent parameters. We show examples of CNTFET simulations and extract from them the fitting parameters of the model. The aim is to achieve a fully functional description in Verilog-A language and create a model library for the SPICE-like simulator environment, in order to be used by IC designers.

Special issue on SoC and AI processors

Special issue on SoC and AI processors

The synthesis method of logic circuits based on the iMemComp gates

The iMemComp is a family of logic gates based on RRAM devices. It has potential advantage on the design of high-performance logic circuits, since the NAND, AND, NOT and transmission iMemComp gates only consume single cycle, respectively. However, the synthesis method of logic circuits based on the iMemComp gates has not been systematically studied before. This work proposes the synthesis method of the row-oriented logic circuits based on the multi-input single-cycle iMemComp gates. The synthesis results show that the circuits generated from the proposed method outperform most of those RRAM based counterparts generated from the previous methods. Furthermore, the synthesis method of the array-oriented iMemComp logic circuits is proposed. The proposed array-oriented method generates the relatively high-performance logic circuits since both the row-based and the column-based single-cycle iMemComp gates are applied, and the generated circuits are relatively area-efficient because the intra-row and inter-row redundancies are utilized in the circuit mapping.

An Improved iMemComp OR Gate and its Applications in Logic Circuits

The iMemComp (Intelligent memristive computing) gates are a family of logic gates based on the RRAM (Resistive Random Access Memory) devices. It has potential advantage for the design of high-performance logic circuits, because the iMemComp NAND, AND, NOT, and transmission gates only consume single cycle, respectively. However, the original two-input iMemComp OR gate, which requires three cycles, is a relatively slow gate. It decreases the performance of some logic circuits. This work proposes an improved iMemComp OR gate with only one cycle and three RRAM cells. Both the circuit performance and area consumption of the full-adder and LFSR circuits are improved by the application of the proposed OR gate. Furthermore, we propose a general synthesis method of logic circuits based on the improved logic gate. The synthesis results show that the circuits generated from the proposed synthesis method outperform the previous RRAM based counterparts for most cases of the MCNC benchmark circuits.

Behavioral Modeling of Photon Arrival Time for Time-of-Flight Measurement Circuit Simulation

This letter proposes a behavioral model to estimate the statistical photon arrival time for time-of-flight (TOF) measurement circuit simulation. A theoretical model is derived to calculate the photon arrival rate by full consideration of a variety of properties of a TOF measurement system, such as laser source, optics, single-photon avalanche diode detector, target distance, and ambient illumination. For the first time, the newly developed model is implemented in behavioral Verilog-A hardware description language and successfully operated on Cadence Spectre simulator for TOF circuit simulation. It is capable of accurately predicting the statistical performance parameters such as photon arrival time and achievable distance, providing a new candidate tool for the ease of design and simulation of various high-performance TOF measurement circuits.

Robustness to Voltage Noise With Ring Oscillator Clocks

Voltage noise is the main source of dynamic variability in integrated circuits and a major concern for the design of power delivery networks (PDNs). Lower supply voltages were made possible with technology scaling, but power density was also increased. Consequently, power integrity became a key factor in the design of reliable high performance circuits. Ring oscillators clocks (ROCs) have been proposed as an alternative to mitigate the negative effects of voltage noise. However, the effectiveness highly depends on the design parameters of the PDN, power consumption patterns, and spatial locality of the ROC within the clock domain. This paper analyzes the impact of the PDN parameters and ROC location on the voltage noise and the robustness achieved by using ROCs. The capability of reacting instantaneously to large voltage droops makes ROCs an attractive solution, which also allows to relax the constraints required for the PDN design. The experiments show that up to 83% of the margins for voltage noise and up to 27% of the total leakage power can be reduced by using ROCs. In addition, PDN simplifications are possible, with fewer power interconnections or package decoupling capacitors of lower quality. Tolerance to voltage noise and related benefits can be increased with multiple ROCs.

Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits

PurposePower consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits.Design/methodology/approachIn this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment.FindingsExperimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits.Originality/valueThe proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

Minimum energy solution for ultra-low power applications

This paper examines device sizing of CMOS inverter circuit at 22-nm technology node using predictive technology model in deep subthreshold region. Channel length (L) of the device is resolved to obtain optimized threshold voltage @ supply voltage of 150 mV. Aspect ratio of Inverter logic gate is determined for the same supply voltage. Symmetrical transient response analysis is performed. It is found that the inverter logic gate is symmetric when aspect ratio (β) is equal to 3.71. Minimum propagation delay is found and observed that high performance circuit design is achievable for higher β ratios. At L = 66 nm, optimum threshold voltage is obtained. Minimum energy point is also obtained at β ratio of 3.71 at 122 mV.

110-GHz Through-Substrate-Via Transition Based on Copper Nanowires in Alumina Membrane

A new through-substrate via (TSV) for millimeter-wave frequencies is proposed. The via is formed by copper nanowires connecting the bottom and top surfaces of a porous alumina membrane. It is shown here that the nanowire via is simple to fabricate using a low-cost technology. The nanowire vias were tested as coplanar waveguide transitions and characterized up to 110 GHz. The results show insertion loss better than 0.37 dB and return loss better than 14 dB per transition at 110 GHz. An electrical model for the vias was derived to give a design tool for circuit designers. These TSVs, along with the high-performance transmission lines already developed on the porous alumina membranes, contribute to a powerful platform for the design of high-performance circuits on this innovative interposer.

Analytical drain current model for symmetric dual-gate amorphous indium gallium zinc oxide thin-film transistors

An analytical drain current model based on the surface potential is proposed for amorphous indium gallium zinc oxide (a-InGaZnO) thin-film transistors (TFTs) with a synchronized symmetric dual-gate (DG) structure. Solving the electric field, surface potential (φS), and central potential (φ0) of the InGaZnO film using the Poisson equation with the Gaussian method and Lambert function is demonstrated in detail. The compact analytical model of current–voltage behavior, which consists of drift and diffusion components, is investigated by regional integration, and voltage-dependent effective mobility is taken into account. Comparison results demonstrate that the calculation results obtained using the derived models match well with the simulation results obtained using a technology computer-aided design (TCAD) tool. Furthermore, the proposed model is incorporated into SPICE simulations using Verilog-A to verify the feasibility of using DG InGaZnO TFTs for high-performance circuit designs.