Abstract
This paper examines device sizing of CMOS inverter circuit at 22-nm technology node using predictive technology model in deep subthreshold region. Channel length (L) of the device is resolved to obtain optimized threshold voltage @ supply voltage of 150 mV. Aspect ratio of Inverter logic gate is determined for the same supply voltage. Symmetrical transient response analysis is performed. It is found that the inverter logic gate is symmetric when aspect ratio (β) is equal to 3.71. Minimum propagation delay is found and observed that high performance circuit design is achievable for higher β ratios. At L = 66 nm, optimum threshold voltage is obtained. Minimum energy point is also obtained at β ratio of 3.71 at 122 mV.
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