Fine-Grained Energy-Constrained Microprocessor Pipeline Design

Abstract

Energy-constrained microprocessor design plays an important role in many emerging Internet of Things platforms operating on harvested or limited energy budget. For this purpose, operating at the supply voltage corresponding to the minimum energy point (MEP) can achieve significant energy savings. However, the MEP voltage is highly dependent on the threshold voltage, the structure, and the activity rate of the circuit. This is more pronounced in pipelined processors as different pipeline stages have different structure with huge intrinsic activity rate variations. Therefore, the energy-saving is limited when only a single MEP voltage is chosen for the entire microprocessor. To address this issue, we propose a fine-grained MEP tuning technique, in which the individual pipeline stages are designed to operate at their MEPs, through per pipeline stage supply and threshold voltage tuning, by considering their activity rates. The proposed optimization is applied to two processors, FabScalar and OpenSPARC, and simulation results show that the proposed technique can improve the energy efficiency of both the cores by almost 50%. The improvement in energy efficiency is obtained at the cost of 6% performance and < 2% area overhead.