Design of 10T full adder cell for ultralow-power applications

Abstract

Abstract This research paper performs symmetrical transient response analysis of FO4 inverter logic gate at 16-nm technology node. It is observed that symmetry is obtained at the aspect ratio (β) is equal to 3.52. With this β ratio, minimum energy point is investigated and found to be 0.15 V. At this minimum energy point, this research paper proposes an ultralow-power 10T 1-bit full adder circuit at 16-nm technology node in subthreshold region for energy constraint applications. It exhibits superior performance in terms of design metrics like propagation delay, average power, leakage power and energy at optimum supply voltage i.e., at 0.15 V. The proposed design achieves 1.81×, 3.39×, 2.25×, and 6.12× improvement in propagation delay, average power dissipation, leakage power dissipation and energy compared to conventional 1-bit full adder circuit. The proposed design exhibits 1.02× improvement in average power variability.