Which is the Best 2-to-1 Line Multiplexer for Ultralow-Power Applications?

Abstract

This paper first investigates the output waveforms of various 2:1 multiplexer (2:1 MUX) circuits in different CMOS (Complementary MOS) logic styles at deep-sub threshold/low-frequency region at 16-nm technology node. It further compares the average power dissipation (taking both dynamic and leakage power into consideration) of those 2:1 MUX circuits which offer reliable output waveform to find out the best CMOS logic style for ultralow-power applications. Finally, the multiplexer circuit dissipating the least average power is implemented using emerging CNFET technology to achieve even better results in terms of different design matrices such as average power dissipation, propagation delay, power-delay product (PDP) and energy-delay product (EDP). CMOS transmission gate (CMOSTG) based circuit is found to dissipate minimum average power among all the other working CMOS logic styles and Simulation results show that its CNFET based realization further improves the output waveform along with reduction in average power dissipation (by 2×), propagation delay (by 1.3×), PDP (by 2.6×) and EDP (by 3.5×) respectively at 130 mV compared to its CMOS counterpart.