High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Mehedi Hasan,Abdul Hasib Siddique,Sharnali Islam,Mainul Hossain,Hasan U Zaman,Abdal Haque Mondol

doi:10.11591/ijeei.v8i4.2582

Abstract

Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors. Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture has been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 26.67 % improvement in speed, 5.966 % improvement in power consumption and 31.06 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.

Highlights

The necessity of high-speed, energy-saving and area-efficient way of arithmetic operations has become the foremost requirements for present-day microprocessors
Architecture of 4-bit Carry Look-Ahead (CLA) process plays an important role in wide adder design since 4-bit adders are used as fundamental units [5]
A 4-bit CLA process in static CMOS logic has been developed in this research work

Summary

INTRODUCTION

The necessity of high-speed, energy-saving and area-efficient way of arithmetic operations has become the foremost requirements for present-day microprocessors. Among high-speed wide adder topologies, the CLA process prevails dominant as the delay occurred due to carry propagation is reduced by computing several stages in parallel [4]. Architecture of 4-bit CLA process plays an important role in wide adder design since 4-bit adders are used as fundamental units [5]. Optimized high-performance design of a 4-bit CLA process will bring about comprehensive performance enhancement in wide adder blocks [6]. Various CLA techniques mainly focused in CLA logic interpretation and algorithms have been developed, only a handful amount of research work has been conducted in transistor level representation of 4-bit CLA. The proposed CLA circuit design computes carry-out bits without using the traditional method of generating carry-generate and carry-propagate terms. Complex transistor networks have been developed in order to reduce delay and power

CONVENTIONAL 4-BIT CLA PROCESS IN STATIC CMOS LOGIC

PROPOSED 4-BIT CARRY LOOK-AHEAD ADDER IN STATIC CMOS LOGIC

SIMULATION RESULT ANALYSIS AND COMPARISON

Findings

CONCLUSION