Abstract
Carbon nanotubes field-effect transistors (CNTFETs) have been recently studied with great interest due to the intriguing properties of the material that, in turn, lead to remarkable properties of the charge transport of the device channel. Downstream of the full-wave simulations, the construction of equivalent device models becomes the basic step for the advanced design of high-performance CNTFET-based nanoelectronics circuits and systems. In this contribution, we introduce a strategy for deriving a compact model for a CNTFET that is based on the full-wave simulation of the 3D geometry by using the finite element method, followed by the derivation of a compact circuit model and extraction of equivalent parameters. We show examples of CNTFET simulations and extract from them the fitting parameters of the model. The aim is to achieve a fully functional description in Verilog-A language and create a model library for the SPICE-like simulator environment, in order to be used by IC designers.
Highlights
An intrinsic carbon nanotube (CNT) under a low voltage bias is characterized by ballistic or near-ballistic transport related to the very long mean free path
Various carbon nanotube FET (CNTFET) models have been reported in recent years [15,16,17,18,19,20,21,22]; some of them use simplifications, making it questionable when evaluating the transient response and device dynamic performance, while other models are described in terms of an integral function that requires intensive calculation efforts, making it difficult to implement in circuit simulators like SPICE
Implementation of the proposed CNTFET architecture and to obtain a Verilog-A description of the final customized virtual source CNTFET SW model suitable for analog circuit design. This can be done through the extraction and modeling of the physical and non-physical parameters of the “base” model starting from experimental data derived from COMSOL simulation of the CNTFET
Summary
An intrinsic carbon nanotube (CNT) under a low voltage bias is characterized by ballistic or near-ballistic transport related to the very long mean free path. In [7], a compact and efficient CNTFET model focusing on both intrinsic and extrinsic device properties (e.g., tunneling current and parasitic capacitances) was firstly introduced for future implementation in SPICE or Verilog-A. It is based on the virtual-source (VS) approach consisting of a semi-empirical model applicable to MOSFETs and depending on a large amount of reproducible data to extract device empirical parameters [8]. The active region, e.g., the channel is an assembly of semiconductive nanotubes, be they single-wall (SW) or multi-wall (MW) In this region, (ii) we solve the Schrödinger equation and derive the charge transport for the CNT layer(s) of given size, chirality, intrinsic doping, and kind of contacts with metal electrodes. Self-consistently, (iv) we extract from the simulation results the physical (geometrical) and non-physical (fitting) parameters for the customized virtual source CNTFET SW model in order to obtain a Verilog-A description of this model suitable for analog circuit design
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