High Output Conductance Research Articles

Signal and Noise of Schottky-Junction Parallel Silicon Nanowire Transducers for Biochemical Sensing

Parallel arrays of silicon nanowire transistors are novel types of transducers under study for chemical and biochemical sensing that exploit the high surface-to-volume ratio of nanowires for sampling of low analyte concentrations and yet provide high output conductance. To investigate the applicability and practical sensitivity of parallel nanowire sensor devices, here, we study their signal-to-noise behavior. Parallel arrays of nominally un-doped Si-nanowires with intruded Ni silicide contacts were characterized by capacitance–voltage, current–voltage, and noise measurements. The power spectral density (PSD) shows a high noise level, which is strongly gate-voltage-dependent. The normalized PSD decreases with the square root of the amount of channel charge, which indicates that the $1/f$ -noise is uncorrelated. Therefore, Hooge’s model can be applied, and $\alpha _{\mathrm {\mathbf {H}}}$ between 7E-1 and 3E-2 is extracted. The input-referred voltage noise of 100 $\mu $ VHz $^{{\mathbf {-0.5}}}$ and a charge noise of 1000 eHz $^{{\mathbf {-0.5}}}$ are obtained at 1 Hz for parallel arrays of approximately 100 nanowires with a 7.4 $\mu \text{m}$ long conduction channel. It is found that the smallest input referred noise level is obtained when operating the device directly at the threshold voltage $\text{V}_{\mathrm {\mathbf {th { }}}}$ independent of the device gate length. Using Al2O3 as ion-sensitive dielectric, the presented devices are employed as pH-sensors. It is found that the Ag/AgCl reference electrode is adding a large level of correlated drift, when used in continuous voltage sweeping mode, which dominates the low-frequency noise.

Hafnium oxide based cylindrical junctionless double surrounding gate (CJLDSG) MOSFET for high speed, high frequency digital and analog applications

In this paper Hafnium Oxide (HfO2) based cylindrical Junctionless Double Surrounding Gate (CJLDSG) MOSFET has been analyzed for various metrics of device performance. HfO2 based CJLDSG MOSFET has been compared with HfO2 based Cylindrical Junctionless Surrounding Gate (CJLSG) MOSFET and Silicon Oxide (SiO2) based CJLDSG MOSFET and CJLSG MOSFET. It has been observed that HfO2 based CJLDSG MOSFET shows improved analog performance in terms of higher drain current, higher transconductance, higher output conductance (gd), higher Transconductance Generation Factor (TGF), higher Early Voltage (VEA), Maximum Transducer Power Gain (MTPG), Current Gain and Subthreshold Slope (SS) close to 60 mV/decade. HfO2 based CJLDSG MOSFET shows lower channel resistance. The Cut Off Frequency (fT) and Frequency Transconductance Product (FTP) of HfO2 based CJLDSG MOSFET is maximum among all and it also offers highest frequency of operation. It also shows higher Ion/Ioff ratio. Thus, making HfO2 based CJLDSG MOSFET an ultimate device for high speed, high frequency digital and analog applications.

Study of Novel Channel Materials Using III-V Compounds with Various Gate Dielectrics

The exponential rise in the density of silicon CMOS transistors has now reached a limit and threatening to end the microelectronics revolution. To tackle this difficulty, group III–V compound semiconductors due to their outstanding electron transport properties and high mobility are very actively being researched as channel materials for future highly scaled CMOS devices. In this paper, we have studied a ballistic nanoscale MOSFET using simulation approach by replacing silicon in the channel by III-V compounds. The channel materials considered are silicon (Si), Gallium arsenide (GaAs), Indium arsenide (InAs), Indium Phosphide (InP) and Indium Antimonide (InSb). The device metrics considered at the nanometer scale are subthreshold swing, Drain induced barrier lowering, on and off current, carrier injection velocity and switching speed. These channel materials have been studied using various dielectric constants. It has been observed that Indium Antimonide (InSb) has higher on current, higher transconductance, idealistic subthreshold swing, higher output conductance, higher carrier injection velocity and comparable voltage gain compared to Silicon, thus, making InSb as a possible candidate to be used as channel material in future nanoscale devices.

Current Saturation in Submicrometer Graphene Transistors with Thin Gate Dielectric: Experiment, Simulation, and Theory

Recently, graphene field-effect transistors (FET) with cutoff frequencies (f(T)) between 100 and 300 GHz have been reported; however, the devices showed very weak drain current saturation, leading to an undesirably high output conductance (g(ds)= dI(ds)/dV(ds)). A crucial figure-of-merit for analog/RF transistors is the intrinsic voltage gain (g(m)/g(ds)) which requires both high g(m) (primary component of f(T)) and low g(ds). Obtaining current saturation has become one of the key challenges in graphene device design. In this work, we study theoretically the influence of the dielectric thickness on the output characteristics of graphene FETs by using a surface-potential-based device model. We also experimentally demonstrate that by employing a very thin gate dielectric (equivalent oxide thickness less than 2 nm), full drain current saturation can be obtained for large-scale chemical vapor deposition graphene FETs with short channels. In addition to showing intrinsic voltage gain (as high as 34) that is comparable to commercial semiconductor FETs with bandgaps, we also demonstrate high frequency AC voltage gain and S21 power gain from s-parameter measurements.

Printed Sub‐2 V Gel‐Electrolyte‐Gated Polymer Transistors and Circuits

AbstractThe fabrication and characterization of printed ion‐gel‐gated poly(3‐hexylthiophene) (P3HT) transistors and integrated circuits is reported, with emphasis on demonstrating both function and performance at supply voltages below 2 V. The key to achieving fast sub‐2 V operation is an unusual gel electrolyte based on an ionic liquid and a gelating block copolymer. This gel electrolyte serves as the gate dielectric and has both a short polarization response time (<1 ms) and a large specific capacitance (>10 µF cm−2), which leads simultaneously to high output conductance (>2 mS mm−1), low threshold voltage (<1 V) and high inverter switching frequencies (1–10 kHz). Aerosol‐jet‐printed inverters, ring oscillators, NAND gates, and flip‐flop circuits are demonstrated. The five‐stage ring oscillator operates at frequencies up to 150 Hz, corresponding to a propagation delay of 0.7 ms per stage. These printed gel electrolyte gated circuits compare favorably with other reported printed circuits that often require much larger operating voltages. Materials factors influencing the performance of the devices are discussed.

A design example of a 65 nm CMOS operational amplifier

AbstractIn this paper, we discuss the properties of new nanometer‐size CMOS technologies being important for the circuit designer. Thereby we concentrate on analogue circuit design. In the literature, the gain reduction by the high output conductance of the transistors is discussed. In detail, we further describe gain reduction due to gate‐leakage current. Finally, we present a design example of a fully differential operational amplifier in a 65 nm CMOS technology including results. Copyright © 2007 John Wiley & Sons, Ltd.

Punch-through in short-channel AlGaN/GaN HFETs

Short-channel punch-through effects are demonstrated in 0.17 /spl mu/m gate length AlGaN/GaN single heterojunction field-effect transistors. These take the form of a high output conductance and the strong dependence of pinch-off voltage on drain voltage. It is shown by simulation that they can be explained by poor confinement of charge at the AlGaN/GaN interface resulting in current flow within the bulk of the GaN layer. This is caused by there being a concentration of only /spl sim/1.5/spl times/10/sup 16/ cm/sup -3/ deep levels in the insulating GaN buffer layer. It is found that a net acceptor density of around 10/sup 17/ cm/sup -3/ is required to ensure suppression of short-channel effects.

InP Hot Electron Transistors with a Buried Metal Gate

To apply the ballistic nature of hot electrons, an InP hot electron transistor with a buried metal (BM-HET) is reported. In this device, carriers are extracted from the emitter by an attractive potential originating from an embedded metal grating, and they propagate through intrinsic semiconductor material only. A simple estimation shows a high cutoff frequency and low output conductance. The estimated highest cutoff frequency is approximately 1 THz. Fabricated devices show that the collector current increased with the gate bias. After extraction of the leakage current, a clear saturation of the collector current in common-emitter characteristics was confirmed and the possibility of BM-HET as a candidate for high-speed electron devices was demonstrated.

Carrier transport related analysis of high-power AlGaN/GaN HEMT structures

Shubnikov-de Haas (SdH) oscillation and Hall measurement results were compared with HEMT DC and RF characteristics for two different MOCVD grown AlGaN-GaN HEMT structures on semiinsulating 4H-SiC substrates. A HEMT with a 40-nm, highly doped AlGaN cap layer exhibited an electron mobility of 1500 cm/sup 2//V/s and a sheet concentration of 9/spl times/10/sup 12/ cm at 300 K (7900 cm/sup 2//V/s and 8/spl times/10/sup 12/ cm/sup -2/ at 80 K), but showed a high threshold voltage and high DC output conductance. A 27-nm AlGaN cap with a thinner, lightly doped donor layer yielded similar Hall values, but lower threshold voltage and output conductance and demonstrated a high CW power density of 6.9 W/mm at 10 GHz. The 2DEG of this improved structure had a sheet concentration of n/sub SdH/=7.8/spl times/10/sup 12/ cm/sup -2/ and a high quantum scattering lifetime of /spl tau//sub q/=1.5/spl times/10/sup -13/ s at 4.2 K compared to n/sub SdH/=8.24/spl times/10/sup 12/ cm/sup -2/ and /spl tau//sub q/=1.72/spl times/10/sup -13/ s for the thick AlGaN cap layer structure, Despite the excellent characteristics of the films, the SdH oscillations still indicate a slight parallel conduction and a weak localization of electrons. These results indicate that good channel quality and high sheet carrier density are not the only HEMT attributes required for good transistor performance.

InAs/AlSb dual-gate HFETs

We report the first implementation of InAs/AlSb dual-gate (DG) HFETs. The devices were fabricated by conventional optical lithography and consist of two electrically distinct 1-μm gates, with a 1-μm intergate separation. The DG-HFETs feature well-behaved, kink-free drain characteristics, and exhibit both high transconductance and low output conductance. We find that DG operation significantly reduces the short-channel effects that have so far plagued InAs/AlSb devices, and increases the maximum allowable drain bias. We estimate that cutoff frequencies as high as 30 GHz-μm may be possible for such devices based on simple equivalent circuit models and previously published experimental data on single-gate InAs/AlSb HFETs.

Effect of bipolar turn-on on the static current-voltage characteristics of scaled vertical power DMOSFET's

The parasitic bipolar transistor inherent in the power vertical Double Diffused MOSFET (DMOSFET) structure can have a significant impact on its performance and reliability. Selectively formed TiSi/sub 2/ films on source contacts were used to reduce the contact resistance to n/sup +/ source diffusion. These devices exhibit "kinks" in the output I-V characteristics. High contact resistance of TiSi/sub 2/ to moderately doped p-body diffusion causes high output conductance. Detailed two-dimensional numerical simulations are used to investigate the effect of the parasitic bipolar transistor on the static characteristics of scaled silicided DMOSFET's. The high contact resistance of TiSi/sub 2/-p-body interface leads to a floating potential and causes significant reduction in the MOS gate threshold voltage and results in a premature bipolar turn-on. It is shown that the parasitic bipolar turn-on places an important constraint on the scalability of the device into the submicron regime. A novel self-aligned DMOSFET structure with a shallow diffused p/sup +/ region is shown to eliminate this effect. Numerical simulations are shown to be in excellent agreement with the measured data at various temperatures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An AC conductance technique for measuring self-heating in SOI MOSFET's

In this paper, we present a new technique for isolating the electrical behavior of an SOI MOSFET's from the self-heating effect using an AC conductance method. This method reconstructs an I-V curve by integrating high frequency output conductance data. The heating effect is eliminated when the frequency is much higher than the inverse of the thermal time constant of the SOI device. We present measurement results from SOI MOSFET's that demonstrate that heating can indeed be significant in SOI devices.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Modeling frequency dependence of GaAs MESFET characteristics

We present a new method of modeling the output conductance dispersion of GaAs MESFET's. High frequency model parameters are extracted and then used to model high frequency output conductance over a wide range of bias conditions. The model is then used to simulate and analyze the effect of output conductance dispersion on the performance of DCFL and SCFL logic gates. Whereas the DCFL performance is not significantly affected by the high frequency effects, the noise margin of SCFL decreases by almost a factor of 30% above 100 kHz, with an associated decrease in the voltage swing and gate delay. >

Impact ionisation in high-output-conductance region of 0.5 μm AlSb/InAs HEMTs

DC and RF measurements on AlSb/InAs HEMTs biased in the commonly observed high output conductance region are reported. In this region, high gate current, inductive output impedance and increased noise were observed resulting from impact ionisation. Devices with a 0.5 μm gate length exhibited a maximum f T and f max of 25 and 40 GHz, respectively

Temperature dependence of common-emitter I-V and collector breakdown voltage characteristics in AlGaAs/GaAs and AlInAs/GaInAs HBT's grown by MBE

Temperature-dependent measurements from 25 to 125 degrees C have been made of the DC I-V characteristics of HBTs with GaAs and In/sub 0.53/Ga/sub 0.47/As collector regions. It was found that the GaAs HBTs have very low output conductance and high collector breakdown voltage BV/sub CEO/>10 V at 25 degrees C, which increases with temperature. In striking contrast, the In/sub 0.53/Ga/sub 0.47/As HBTs have very high output conductance and low BV/sub CEO/ approximately 2.5 V at 25 degrees C, which actually decreases with temperature. This different behavior is explained by the >10/sup 4/ higher collector leakage current, I/sub CO/, in In/sub 0.53/Ga/sub 0.47/As compared to GaAs due to bandgap differences. It is also shown that device self-heating plays a role in the I-V characteristics.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Optimization of buffer layers for AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistors by atmospheric pressure metalorganic chemical vapor deposition

Pseudomorphic AlGaAs/InGaAs/GaAs high electron mobility transistors (HEMT) incorporating various types of buffer layers were fabricated (D = 0.50 × 100μm) and characterized by Hall-effect measurements, low temperature photoluminescence (PL), and room temperature IV characteristics. The devices fabricated with a thick (5000A) undoped high purity GaAs buffer layer grown at 650° C showed poor pinch-off characteristics, high output conductance and large leakage currents (>2 mA at pinch-off). Devices incorporating an undoped high purity GaAs (3000A) buffer layer grown at 550° C showed sharp pinch-off characteristics, low output conductance, and low leakage currents (1.3 mA at pinch-off). Low temperature growth of GaAs (550° C) enhanced carbon incorporation resulting in increasedp-type characteristics. This type of buffer layer provided additional barrier height between the active layer and the substrate reducing the injection of electrons into the substrate.

Impact of buffer layer design on the performance of AlInAs-GaInAs HEMTs

The authors report a study of the impact of buffer layer design on the characteristics of Al/sub 0.48/In/sub 0.52/As-Ga/sub 0.47/In/sub 0.53/As HEMTs (high-electron-mobility transistors). The aim of the study is to understand and correct the problem of high output conductance observed in devices with a high transconductance. Devices with 1.0- mu m gate lengths were fabricated using modulation-doped Al/sub 0.48/In/sub 0.52/As-Ga/sub 0.47/In/sub 0.53/As epitaxial layers which had sheet charge densities between 3*10/sup 12/ and 3.5*10/sup 12/ cm/sup -2/ and mobilities at 300 K between 9000 and 10000 cm V/sup -1/ S/sup -1/. The different buffer layer designs used were: (1) a standard undoped Al/sub 0.48/In/sub 0.52/As buffer 250-nm-thick; (2) an Al/sub 0.48/In/sub 0.52/As buffer with a 20-AA thick highly doped p-type region 50 AA below the channel; (3) a Ga/sub 0.47/In/sub 0.53/As buffer with a 20-AA-thick highly doped p-type region below the channel; and (4) a low-temperature AlInAs buffer layer. The device with the low-temperature AlInAs had the best output characteristics, signifying that it was the best mode of confining electrons in the channel.

Excess drain current in heterojunction FETs due to substrate space-charge-limited current

A comparison of gated and ungated heterostructure FETs shows that high output conductance, poor pinchoff, and kinks in the I-V characteristics of heterojunction FETs (HFETs) are related to space-charge-limited conduction (SCLC) associated with deep traps in the substrate. The dominant trap level was determined from I-V measurements of an ungated structure as a function of temperature and the trap density was determined from SCLC characteristics. Reduction in excess drain current can be achieved by using a high trap concentration substrate and by increasing the electron barrier between the channel and the substrate. >

0.5- mu m gate length self-aligned gate MODFET with reduced short-channel effects

Reduced short-channel effects were obtained by using a buried AlGaAs layer beneath the channel. A 0.5*10- mu m/sup 2/ MODFET was fabricated that had a peak transconductance of 264 mS/mm with a K-factor of 425 mA/V/sup 2/-mm. The measured output conductance was 2.37 mS/mm, a reduction from 18 mS/mm for a 0.5- mu m device without the buried layer. This combination of high transconductance and low output conductance makes the device ideal for high-speed analog and digital applications. The reduced output conductance gives a maximum gain of 110, compared with a more typical gain of 25 for a standard 0.5- mu m MODFET device. Threshold voltage dependence on gate length decreases from a 60-mV shift for 1.5- to 0.5- mu m gate length to 20 mV over the same range. The structure of the device, which was grown by molecular-beam epitaxy, consists of a five-period AlGaAs/GaAs superlattice and AlGaAs cap and spacer layers. The GaAs conducting channel is located between this charge control layer and a buried AlGaAs channel confinement buffer layer. This double heterostructure forms a quantum well in the channel region to further confine the quasi-two-dimensional electron gas. >

A vertical-junction field-effect transistor

A vertical JFET structure is described which allows realization of submicrometer channel-length devices using standard photolithographic techniques. The fabrication procedure utilizes an anisotropic etch followed by an impurity diffusion or implantation to define the channel. A numerical simulation of the JFET operation is implemented using a finite-element analysis technique. Typical devices exhibit high-output conductance and a tendency to resist channel pinchoff at the drain end. Etched bipolar transistors having current gains as high as 400 can also be formed concurrently with the fabrication of the vertical JFET structures.