Abstract
AbstractIn this paper, we discuss the properties of new nanometer‐size CMOS technologies being important for the circuit designer. Thereby we concentrate on analogue circuit design. In the literature, the gain reduction by the high output conductance of the transistors is discussed. In detail, we further describe gain reduction due to gate‐leakage current. Finally, we present a design example of a fully differential operational amplifier in a 65 nm CMOS technology including results. Copyright © 2007 John Wiley & Sons, Ltd.
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