High-order Sigma-delta Modulator Research Articles

Systematic design of stable high-order delta sigma modulators using genetic algorithm

Systematic design of stable high-order delta sigma modulators using genetic algorithm

Implementation and Performance Evaluation of the Frequency-Domain-Based Bit Flipping Controller for Stabilizing the Single-Bit High-Order Interpolative Sigma Delta Modulators

This paper is an extension of the existing works on the frequency-domain-based bit flipping control strategy for stabilizing the single-bit high-order interpolative sigma delta modulator. In particular, this paper proposes the implementation and performs the performance evaluation of the control strategy. For the implementation, a frequency detector is used to detect the resonance frequencies of the input sequence of the sigma delta modulator. Then, a neural-network-based controller is used for finding the solution of the integer programming problem. Finally, the buffers and the combinational logic gates as well as an inverter are used for implementing the proposed control strategy. For the performance evaluation, the stability region in terms of the input dynamical range is evaluated. It is found that the control strategy can significantly increase the input dynamical range from 0.24 to 0.58. Besides, the control strategy can be applied to a wider class of the input signals compared to the clipping method.

A Fractional-Order Noise-Shaping Integrator for Sigma-Delta Modulator

A novel fractional-order Sigma-Delta modulator, which can improve the signal to noise ratio (SNR) and is of robust stability of a high order Sigma-Delta modulator, is presented in the paper. Traditional Sigma-Delta modulator mainly focused on forming an integer high order integrator to improve the SNR, whereas the paper presents a fractional-order integrator instead to obtain higher SNR and better stability. Specifically, a 4th order digital integrator and a fractional-order PIλ controller are inserted between the AFE and the quantizer. The 4th order digital integrator increases overall loop order to produce much higher SNR for Sigma-Delta modulator and the fractional-order PIλ controller allows fine tuning accuracy in seeking the coefficients for Sigma-Delta modulator and provides stability in the placement of poles and zeros for compensating the phase delays caused by system nonlinearity. The parameters of PIλ controller are optimized by using swarm intelligent optimization algorithm. The stability of the proposed fractional-order Sigma-Delta modulator is analyzed and the robustness of the proposed fractional-order Sigma-Delta modulator is demonstrated. Further simulation from the fractional-order Sigma-Delta modulator, results of SNR>145dB and the noise floor under -190dB are obtained in frequency range of [5-150Hz].

Performance improvement of a sigma-delta modulator using fractional-order disturbance observer

This paper proposes a novel design of a high order closed-loop Sigma-Delta modulator using a fractional-order disturbance observer, which can reduce the influence of possible dispersions of the sensing element and offset the effect of the external disturbance. The proof mass can maintain near its position of equilibrium by using the proposed fractional-order disturbance observer, which ensures a better control of the proof mass displacement, and the small proof mass displacement can enhance the sensor resolution and the overall system performance. Fractional-order disturbance observer possesses stronger robust stability of interference elimination, because the introduction of fractional calculus makes Q-filter expanding from an integer domain to a real-number domain. Experimental results from the proposed architecture shows an increase of more than 2X improved in signal quantization noise ratio compared to the pure high-order closed-loop Sigma-Delta modulator, and also the proposed Sigma-Delta modulator with a fractional-order disturbance observer improves the performance of disturbance attenuation and system robustness.

Realization of a high-order delta-sigma modulator based on sliding mode control theory

Realization of a high-order delta-sigma modulator based on sliding mode control theory

Improving performance of mobile fronthaul architecture employing high order delta-sigma modulator with PAM-4 format.

An improved high-order delta-sigma modulator with multi-level quantizer is proposed to enable carrier aggregation of 4G-LTE signals in mobile fronthaul. Different from conventional delta-sigma modulation-based digital mobile fronthaul, a 2-bit quantizer is employed to reduce the quantization noise, which enabling the transmission via PAM-4 based IM-DD channel. Moreover, we employ the 4th-order high-pass filter (HPF) to replace the 1st-order HPF in the conventional delta-sigma modulator, resulting in a much better noise shaping performance. In the experiment, a PAM-4 based mobile fronthaul transmission of 32 aggregated 4G-LTE signals with a CPRI equivalent data rate of 39.32-Gb/s is demonstrated in a single-λ 10-Gb/s IM-DD channel. Significant improvement of 68% is achieved in the average EVM performance compared to the previous delta-sigma modulation-based digital mobile fronthaul.

A closed-loop Sigma-Delta modulator for a tunneling magneto-resistance sensor

In this paper, a high-order Sigma-Delta (ΣΔ) modulator in a standard 0.5 µm CMOS technology for a tunneling magneto-resistance sensor (TMR) is presented. The digital output is attained by the interface circuit based on a low-noise chopper front-end and a back-end forth-order Sigma-Delta modulator. The low-noise front-end detection circuit is proposed with correlated double sampling (CDS) technique to eliminate the 1/f noise and offset of operational amplifier. The even harmonics is eliminated by fully differential structure. The interface is fabricated in a standard 0.5 µm CMOS process and the active circuit area is about 4 × 3 mm2. The modulator chip consumes 9.6 mW from a 5 V supply and the sampling frequency is 6.4 MHz. The modulator can achieve a signal-to-noise ratio (SNR) of 121 dB, an effective number of bits 19.85 bits and a harmonic distortion of 113 dB.

Hardware-Efficient Delta Sigma-Based Digital Signal Processing Circuits for the Internet-of-Things

This paper presents hardware-efficient Delta Sigma linear processing circuits for the next generation low-power VLSI devices in the Internet-of-things (IoT).We first propose the P-N (positive-negative) pair method to manipulate both the analog value and length of a first-order Delta Sigma bit sequence. We then present a binary counter method. Based on these methods, we develop Delta Sigma domain on-the-fly digital signal-processing circuits: the Delta Sigma sum adder, average adder and coefficient multiplier. The counter-based average adder can work with both first-order and higher-order Delta Sigma modulators and can also be used as a coefficient multiplier. The functionalities of the proposed circuits are verified by MATLAB simulation and FPGA implementation. We also compare the area and power between the proposed Delta Sigma adders and a conventional multi-bit adder by synthesizing both circuits in the IBM 0.18-μm technology. Synthesis results show that the proposed Delta Sigma processing circuits can extensively reduce circuit area and power. With 100 inputs, a Delta Sigma average adder saves 94% of the silicon area and 96% of the power compared to a multi-bit binary adder. The proposed circuits have the potential to be widely used in future IoT circuits.

A High-Order Sigma-Delta Modulator Applied in Micro-Accelerometer

In this paper a high-order sigma-delta modulator applied in micro-accelerometer is designed. The modulator chooses the distributed feedback structure. And the signal bandwidth is 500Hz, the oversampling ratio is 250 and sampling frequency is 250KHz. By the MATLAB Simulink simulation, when the input signal is 1g, and the signal frequency is 250Hz, the simulation result is that the noise level is-160dBV at the signal frequency in the ideal situation. And when considering the non-ideal factors, the simulation result shows that the noise level at the input accelerated signal is 20dBV higher than the ideal. The overall circuit was implemented under 0.5 um CMOS process and simulated in Cadence Spectre. The final simulation results show that the signal to noise ratio (SNR) is 97.1dB.

Nonlinear Model-Based Approach for Accurate Stability Prediction of One-Bit Higher-Order Delta–Sigma Modulators

The current approaches on predicting the stability of delta-sigma (Δ-Σ) modulators are mostly confined to dc inputs. This poses limitations as practical applications of Δ-Σ modulators involve a wide range of signals other than dc. In this paper, a quasi-linear model for Δ-Σ modulators with nonlinear feedback control analysis is presented, which accurately predicts the stability of higher-order single-loop 1-bit Δ-Σ modulators for various types of input signals, such as single sinusoids, dual sinusoids, multiple sinusoids, and Gaussian. Theoretical values are shown to match closely with simulation results. The results of this paper would significantly speed up the design and evaluation of higher-order single-loop 1-bit Δ-Σ modulators for various applications, including those that may require multiple-sinusoidal inputs or any general input composed of a finite number of sinusoidal components, circumventing the need to perform detailed time-consuming simulations to quantify stability limits. By using the proposed method, the difference between the predicted and the actual stable amplitude limits results in an error of less than 1 dB in the in-band signal-to-noise ratio for the third-order and higher-order Δ-Σ modulators for single-sinusoidal inputs. For single-sinusoidal, dual-sinusoidal, multiple-sinusoidal, and Gaussian inputs, the error is less than 2 dB for the fifth-order modulator and reduces to less than 1 dB for the sixth-order and higher-order Δ-Σ modulators.

Optimal Design for Delta–Sigma Modulators With Root Loci Inside Unit Circle

Single-stage high-order delta-sigma modulators (DSMs) designed by methods with root loci inside the unit circle (RLiUC) can operate stably with full-scale input. The previously published RLiUC method uses a conservative approach to design the loop filter's transfer function H(z) of a DSM, thus resulting in a modest SNR. In this brief, the pole-zero locations of H(z) are optimized to maximize the stable input range while minimizing SNR reduction. Accordingly, optimal third- and fourth-order RLiUC DSMs are designed, and a systematic method for orders higher than 4 is developed. The considerations for the optimal design are the in-band noise attenuation and out-of-band gain of RLiUC DSMs. With an oversampling ratio of 32 and a quantizer bit number of 6, the optimized fourth-order RLiUC DSM achieves a peak SNR of 109 dB. Compared with the previously published result, the SNR is improved by 20 dB. To demonstrate the advantage of RLiUC DSMs, an application example for a class-D amplifier is used. With the RLiUC DSM, the achieved low-distortion output power of class-D amplifiers can be maximized.

Design of A high performance low-power consumption discrete time Second order Sigma-Delta modulator used for Analog to Digital Converter

This paper presents the design and simulations results of a switched-capacitor discrete time Second order Sigma-Delta modulator used for a resolution of 14 bits Sigma-Delta analog to digital converter. The use of operational amplifier is necessary for low power consumption, it is designed to provide large bandwidth and moderate DC gain. With 0.35µm CMOS technology, the S? modulator achieves 86 dB dynamic range, and 85 dB signal to noise ratio (SNR) over an 80 KHz signal bandwidth with an oversampling ratio (OSR) of 88, while dissipating 9.8mW at ±1.5V supply voltage.

Accurate stability prediction of one-bit higher-order delta–sigma modulators for multiple-sinusoidal inputs

The present approaches on predicting stability of delta-sigma (Δ-Σ) modulators are mostly confined to DC inputs. This poses limitations as practical applications of Δ-Σ modulators involve a wide range of signals other than DC such as multiple-sinusoidal inputs for speech modelling. In this study, a quasi-linear model for Δ-Σ modulators with non-linear feedback control analysis is presented that accurately predicts stability of single-loop one-bit higher-order Δ-Σ modulators for multiple sinusoids. Theoretical values are shown to match closely with the simulation results. The results of this study would significantly speed up the design and evaluation of higher-order single-loop Δ-Σ modulators with increased dynamic ranges for various applications that require multiple-sinusoidal inputs or any general input composed of a finite number of sinusoidal components.

A Noise Filtering Technique for Fractional-$N$ Frequency Synthesizers

A noise filtering technique for fractional-N frequency synthesizers (FNFSs) is presented. The noise filter is based on an integer-N (N = 1) phase-locked loop that is placed in a feedback path of an FNFS. By adopting the noise filter, out-of-band quantization noise of a high-order delta-sigma modulator is suppressed. In addition, folded noise due to nonlinearity of a phase/frequency detector (PFD) and a charge pump is improved by reducing phase errors at PFDs. An FNFS using the noise filter is fabricated in 90-nm complementary metal-oxide-semiconductor technology. Its die area is 950 by 950 μm, and its power consumption is 30 mW for a supply voltage of 1 V. The frequency resolution of this FNFS is less than 1 Hz.

A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator

Conventional continuous-time (CT) delta-sigma (¿¿) analog-to-digital converters (ADCs) consume large amount of power in operational amplifiers of a loop-filter. We propose a new loop-filter with single-opamp resonator, ringing-relaxation filter and passive resistor adder to lower power consumption. These three techniques are essential for designing high-order delta sigma modulators with low oversampling ratio. Because the new resonator reduces the number of opamps, the resistor adder displaces a conventional active adder and the ringing-relaxation filter alleviates the burden on the first opamp by reducing its gain bandwidth, FOM is greatly improved. To demonstrate the concept, 300 MHz, fifth-order low-pass, 3-bit CT¿¿ ADC of single feedback with feedforward architecture was implemented in a 1.1 V, 110 nm 1P6M CMOS process. An SNR of 68.2 dB and an SNDR of 62.5 dB were measured in a 10 MHz bandwidth and FOM was 0.24 pJ/conv.

Frequency synthesis using digital-to-frequency conversion and filtering

A novel topology for frequency synthesis using digital-to-frequency conversion and a filtering technique is presented. The implementation uses a high-order digital sigma-delta modulator to encode a DC value, which is then mapped to a corresponding frequency using a digital-to-frequency conversion algorithm. The output bit-sequence with the sigma-delta encoded frequency is then applied to a high-order phase-locked loop (PLL) behaving as a filter operating on the incoming instantaneous frequency. The theory of the proposed scheme is described and validated with simulation and experiment. A prototype board-level implementation with a sixth-order PLL was constructed and frequencies ranging from 30.5 to 44.5 MHz were experimentally generated with a 25 kHz resolution from a single 100 MHz master clock.

A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops

A finite-modulo fractional-N PLL utilizing a low-bit high-order DeltaSigma modulator is presented. A 4-bit fourth-order DeltaSigma modulator not only performs non-dithered 16-modulo fractional-N operation but also offers less spur generation with negligible quantization noise. Further spur reduction is achieved by charge compensation in the voltage domain and phase interpolation in the time domain, which significantly relaxes the dynamic range requirement of the charge pump compensation current. A 1.8-2.6 GHz fractional-N PLL is implemented in 0.18 mum CMOS. By employing high-order deterministic DeltaSigma modulation and hybrid spur compensation, the spur level of less than -55 dBc is achieved when the ratio of the bandwidth to minimum frequency resolution is set to 1/4. The prototype PLL consumes 35.3 mW in which only 2.7 mW is consumed by the digital modulator and compensation circuits.

Comb-Based Decimation Filters for $\Sigma \Delta$ A/D Converters: Novel Schemes and Comparisons

This paper proposes several novel decimation filtering schemes tailored to the design of SigmaDelta analog-to-digital (A/D) converters. On the one hand, it extends the class of modified-sinc filters introduced by Lo Presti, in order to obtain decimation filters capable of decoding high-order SigmaDelta modulators, say up to the fifth order; on the other hand, it introduces the class of sharpened-modified comb filters (SMCF) aimed at increasing the rejection of the SigmaDelta quantization noise around the folding bands and reducing the passband drops of the designed decimation filters with respect to the classic comb structures. Design criteria leading to optimized structures are described. The paper compares classic comb filters with modified and SMCF in terms of performance metrics widely adopted for comb filters. Finally, it derives the maximum SigmaDelta modulator order decodable by any proposed filter cell in the class of the SMCFs

Micromachined Vibratory Gyroscopes Controlled by a High-Order Bandpass Sigma-Delta Modulator

This work reports on the design of novel closed-loop control systems for the sense mode of a vibratory-rate gyroscope based on a high-order sigma-delta modulator (SigmaDeltaM). A low-pass and two distinctive bandpass topologies are derived, and their advantages discussed. So far, most closed-loop force-feedback control systems for these sensors were based on low-pass SigmaDeltaM's. Usually, the sensing element of a vibratory gyroscope is designed with a high quality factor Q to increase the sensitivity and, hence, can be treated as a mechanical resonator. Furthermore, the output characteristic of vibratory rate gyroscopes is narrowband amplitude-modulated signal. Therefore, a bandpass SigmaDeltaM is a more appropriate control strategy for a vibratory gyroscope than a low-pass SigmaDeltaM. Using a high-order bandpass SigmaDeltaM, the control system can adopt a much lower sampling frequency compared with a low-pass SigmaDeltaM while achieving a similar noise floor for a given oversampling ratio (OSR). In addition, a control system based on a high-order bandpass SigmaDeltaM is superior as it not only greatly shapes the quantization noise, but also alleviates tonal behavior, as is often seen in low-order SigmaDeltaM control systems, and has good immunities to fabrication tolerances and parameter mismatch. These properties are investigated in this study at system level

An approach for stability analysis of a single-bit high-order digital sigma-delta modulator

In this work we considered the stability of a single-bit high-order sigma-delta modulator under dc input. A new approach for stability analysis is proposed. A nonlinear circle map is suggested to model the dynamics of the modulator. An analogy between the dynamics of the sigma-delta modulator and the sinusoidal digital phase-locked loop (DPLL) is studied and an approximate fixed point solution is presented with stability criteria. Suggestions for designing stabilized high-order systems are presented.