Abstract
Conventional continuous-time (CT) delta-sigma (¿¿) analog-to-digital converters (ADCs) consume large amount of power in operational amplifiers of a loop-filter. We propose a new loop-filter with single-opamp resonator, ringing-relaxation filter and passive resistor adder to lower power consumption. These three techniques are essential for designing high-order delta sigma modulators with low oversampling ratio. Because the new resonator reduces the number of opamps, the resistor adder displaces a conventional active adder and the ringing-relaxation filter alleviates the burden on the first opamp by reducing its gain bandwidth, FOM is greatly improved. To demonstrate the concept, 300 MHz, fifth-order low-pass, 3-bit CT¿¿ ADC of single feedback with feedforward architecture was implemented in a 1.1 V, 110 nm 1P6M CMOS process. An SNR of 68.2 dB and an SNDR of 62.5 dB were measured in a 10 MHz bandwidth and FOM was 0.24 pJ/conv.
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