High On-state Current Research Articles

Investigation of a Ge-Source Vertical TFET With Delta-Doped Layer

In this article, a $\delta $ -doped germanium-source vertical TFET (Ge-source vTFET) is proposed and investigated by Synopsis TCAD simulation. Higher ON-state current is obtained as the electron tunneling takes place in a direction parallel to the gate electric field. The incorporation of the $\delta $ -doped layer in the germanium source region further reduces the OFF-state leakage current. The impact on the variation of the device geometric dimensions has been studied for various electrical parameters and the dimensions are optimized accordingly through extensive simulations. A very high current ratio of the order ~1011 with a substantially low average subthreshold swing of 21.2 mV/decade is achieved. Benchmarking of the proposed Ge-source vTFET with other novel TFETs is carried out which produced better results in terms of high ON -state current and SSavg. The results obtained for the proposed vTFET make it a potential candidate for ultralow-power applications.

Nanotube Tunneling FET With a Core Source for Ultrasteep Subthreshold Swing: A Simulation Study

In this article, we propose a novel nanotube (NT) tunneling field-effect transistor with a core source (CSNT-TFET) which uses line tunneling. We systematically investigate the CSNT-TFET with the help of calibrated 3-D simulations and demonstrate that it outperforms the conventional NT-TFET in terms of both static and dynamic performance. We show that the CSNT-TFET exhibits a reduced average subthreshold swing (SS) of 33 mV/decade with Ge-source for more than eight orders of magnitude of drain current at an ultralow supply voltage ( ${V}_{\text {DS}}= {0.3}$ V). In addition, the ON-state current of the CSNT-TFET is enhanced by ~13 times with Si-source and by ~6 times with Ge-source even at ${V}_{\text {DS}}= {V}_{\text {GS}}= {0.3}$ V when compared with the NT-TFET. Without the use of any exotic material for the source and channel regions, the CSNT-TFET offers an impact ionization MOS-like steep SS (a minimum SSpoint of ~1 mV/decade) and a high ON-state current of ~10−6 A for ${V}_{\text {DS}}= {V}_{\text {GS}}= {0.3}$ V. Furthermore, the impact of the gate sidewall spacer and source diameter on the performance of the CSNT-TFET is also investigated.

Optimization of Doping Profiles in Insulated-Gate Bipolar-Transistors Using a Large Scale Optimization Technique

There is much interest on the numerical and practical optimization of the doping profiles in semiconductor devices. This interest is mostly driven by the power semiconductor industry, which is in continuous search for higher breakdown voltage semiconductor switches that have lower on-state resistance, and high current handling capacity and switching speeds. Among the existing power semiconductor devices, insulated-gate bipolar-transistors (IGBTs) are becoming more and more attractive because of their high blocking voltage capabilities and on-state current. Although these devices suffer from a relatively lower switching speed compared to current state-of-the-art metal-oxide-semiconductor field-effect-transistors, IGBTs have already become the preferred switching devices in many power applications, such as induction heating applications, traction motors, etc. [1]. In this work we present numerical finite element optimization results for a realistic 70 mm-wide punch-through IGBT structure. The optimization focusses on the two-dimensional doping distribution of the gate, emitter and collector junctions, and of the drift and buffer layers in order to increase the breakdown voltage of the IGBT. The optimization method is based on an adjoint space technique that our group has recently developed for the design of nanoscale semiconductor devices, and which is adjusted here to compute the doping sensitivity functions of the breakdown voltage and on-state resistance in IGBTs [2-4]. These doping sensitivity functions show how sensitive the breakdown voltage and on-state resistance are when we add one additional acceptor or donor impurity at a particular location inside the semiconductor. Since the doping sensitivity functions provide information about the gradient of the breakdown voltage and on-state resistance with respect to the doping concentration they are instrumental for the numerical and practical optimization of IGBTs. As we will show at the conference, we are able to increase the breakdown voltage from approximately 300 V to over 700 V without deteriorating the on-state resistance of the transistor. In the full presentation we will describe how the adjoint method can be used to calculate the doping sensitivity functions of the breakdown voltage, on-state current and voltage, and on-state resistance. We will also present details about the numerical implementation of the optimization method, which is based on a modified gradient optimization appropriate for semiconductor devices. Note that most traditional optimization approaches such as the steepest descends method, the Broyden–Fletcher–Goldfarb–Shanno algorithm, or similar algorithms fail because of the doping concentration varies over many orders of magnitude, which vary can from region to region inside the same device.

Memory Switching and Threshold Switching in a 3D Nanoscaled NbOX System

The 3D crossbar arrays provide a cost-effective approach for high-density integration of resistive switching random-access memory (RRAM). A selector device or self-selective cells can be used to inhibit the sneaking current from the unselected cells. The coexistence of memory switching (MS) with inherent nonlinearity and threshold switching (TS) with high current density in an individual material system will lead to technological benefits for memory integration and neuromorphic computing. However, the reported conductive filament (CF)-type MS and TS combining devices cannot meet the requirements for practical applications, as these devices lack built-in nonlinearity in memory mode and display low current density and large relaxing time in the selector mode. In this letter, we report a 3D TiN/TiO2/NbOX/Pt device with MS and TS before and after the forming processes. In the MS mode, this device shows >50 nonlinearity, a 100 ON/OFF ratio, non-volatility, and stable homogeneous switching due to vacancy redistribution. In the TS mode, owing to the metal–insulator transition, a high ON-state current (1.6 MA/cm 2), high switching speed (<40 ns), and low relaxation time (<50 ns) are observed.

Vertical, electrolyte-gated organic transistors show continuous operation in the MA cm-2 regime and artificial synaptic behaviour.

Until now, organic semiconductors have failed to achieve high performance in highly integrated, sub-100 nm transistors. Consequently, single-crystalline materials such as single-walled carbon nanotubes, MoS2 or inorganic semiconductors are the materials of choice at the nanoscale. Here we show, using a vertical field-effect transistor design with a channel length of only 40 nm and a footprint of 2 × 80 × 80 nm2, that high electrical performance with organic polymers can be realized when using electrolyte gating. Our organic transistors combine high on-state current densities of above 3 MA cm-2, on/off current modulation ratios of up to 108 and large transconductances of up to 5,000 S m-1. Given the high on-state currents at such large on/off ratios, our novel structures also show promise for use in artificial neural networks, where they could operate as memristive devices with sub-100 fJ energy usage.

A comparison of performance between double-gate and gate-all-around nanowire MOSFET

&lt;span lang="EN-MY"&gt;Due to the rapid scaling of &lt;/span&gt;&lt;span&gt;Complementary Metal-Oxide-Semiconductor&lt;/span&gt;&lt;span lang="EN-MY"&gt; (CMOS), the structure of the planar MOSFET approaches the scaling limits when the short channel effects (SCEs) become the main problem. The Double-Gate and Gate-all-Around nanowire MOSFETs are said to be the promising candidate to replace the planar MOSFET in order to pursue CMOS scaling. Therefore, this paper present the result of device simulation using Silvaco TCAD tools for Double-Gate and Gate-All-Around nanowire MOSFETs. The purpose of this simulation work is to compare the performance of GAA nanowire and DG MOSFET and then study the effect of physical parameter on electrical behavior for both devices. The result of the simulated model of Gate-All-Around nanowire is compared with published data. It was found that when the gate length of DG was scaled from 80nm to 10nm, the subthreshold slope is increasing from 62mV/dec to 162.7mV/dec. While for GAA, the subthreshold slope is increasing from 65.8mV/dec to 127mV/dec. The threshold voltage in DG and GAA at Lg=80nm are 0.40646V and &lt;/span&gt;&lt;span&gt;-0.17505V &lt;/span&gt;&lt;span lang="EN-MY"&gt;respectively. Even though heavy doping was good for suppressing SCE, the lower doping concentration is desirable as the DG and GAA nanowire had higher on-state currents with 1.42x10&lt;sup&gt;-3&lt;/sup&gt;Aand 3.23x10&lt;sup&gt;-4&lt;/sup&gt;A respectively. It also showed that the threshold voltage of DG and GAA nanowire increase from -0.0734V to 0.2312V and -0.0319V to 0.2232V respectively when the channel doping is varies from lower to higher concentration.&lt;/span&gt;

Investigation of the Scalability of Emerging Nanotube Junctionless FETs Using an Intrinsic Pocket

The detrimental lateral band-to-band tunneling (L-BTBT) governing the OFF-state performance of the junctionless (JL) FETs is more pronounced in emerging Nanotube (NT) transistor architectures. This restricts the scaling of NT JLFETs irrespective of their ultimate electrostatic gate control due to additional core gate. Therefore, in this paper, we propose a symmetric intrinsic pocketed Pi-NT JLFET which has narrow intrinsic pockets on both sides of the channel region leading to a diminished L-BTBT induced lateral parasitic BJT action in the emerging NT JLFETs. Using calibrated 3-D simulations, we demonstrate that the incorporation of an intrinsic pocket decreases the OFF-state current by around 2 orders of magnitude in the Pi-NT JLFET for a gate length of 20 nm, leading to a significant ON-state to OFF-state current ratio ( $I_{\text{ON}}/I_{\text{OFF}}$ ) of 108. Furthermore, we also show an improvement in the performance of the emerging NT junctionless accumulation mode (JAM) FETs which exhibits a degraded performance compared to NT JLFETs due to enhanced L-BTBT irrespective of their higher ON-state current. The inclusion of the intrinsic pockets in NT JAMFET (Pi-NT JAMFET) reduces the L-BTBT originated OFF-state by 3 orders of magnitude for a gate length of 20 nm leading to an impressive $I_{\text{ON}}/I_{\text{OFF}}$ ratio of 108. Moreover, the proposed Pi-NT JLFET and Pi-NT JAMFET exhibit an impressive $I_{\text{ON}}/I_{\text{OFF}}$ ratio of ~ 108 and 106, respectively, with more than 4 orders of remarkable reduction in the leakage current even when the gate length is scaled to 10 nm. Additionally, the proposed architectures exhibit lower sensitivity to the gate length modulation unlike their conventional counterpart. The Pi-NT transistors exhibit superior immunity against the short channel effects of threshold-voltage roll-off due to the reduced electrostatic source/channel-to-drain coupling. Furthermore, we show that incorporating gate engineering of the dual-material gate (DMG) further enhances the performance of the Pi-NT transistor. The DMG-Pi-NT transistors exhibit an enhanced $I_{\text{ON}}/I_{\text{OFF}}$ ratio ~ 1011 achievable with the proper tuning of the dual metal gate work functions. Thus, our proposed device architecture enhances the scalability of the NT JLFETs and NT JAMFETs for realizing them in the future technology nodes.

First evidence of superiority of Si nanonet field effect transistors over multi-parallel Si nanowire ones in view of electrical DNA hybridization detection

Si nanonets (SiNN, networks of randomly oriented Si nanowires) and multi-parallel silicon nanowires (MP-SiNW) were integrated into field effect transistor using standard and low cost microelectronic technologies. The SiNN field effect transistors exhibit high initial ON-state current (in the range of 10–7 A), ION/IOFF ratio up to 104 and rather homogeneous transfer characteristics. In contrast, the MP-SiNW ones present smaller modulation between ON and OFF currents, higher IOFF and more scattered electrical characteristics. In view of DNA hybridization detection, a simple and eco-friendly functionalization process with glycidyloxypropyltrimethoxysilane (GOPS) was used to covalently graft single strand DNA probes on both SiNN and MP-SiNW devices. Validated by fluorescence measurement, DNA hybridization leads to a systematic decrease of ON-state current of SiNN devices. In addition, SiNN-based sensors exhibit more homogeneous and reproducible current variation in response to DNA hybridization step as compared to MP-SiNW configuration. This result highlights the better sensing performances of SiNN FETs as compared to MP-SiNW ones and emphasizes the SiNN potential for label-free detection of DNA.

The Understanding of SiNR and GNR TFETs for Analog and RF Application With Variation of Drain-Doping Molar Fraction

The 1-D nanoribbon (NR) of monolayer materials has gained immense interest due to their unique properties qualitatively distinct from their bulk properties and the demand for nanoscale applications. In this paper, the quantum transport properties of two most prominent 2-D materials, i.e., silicene NR (SiNR) and a graphene NR (GNR) tunnel field-effect transistor (TFET) with the effect of different dopant molar fractions in the drain region are studied numerically using nonequilibrium Green’s function formalism. In SiNR TFET, higher on-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) is observed due to wider tunneling energy window and high transmission probability of carriers. In order to observe the effect of variation of doping density in the drain region, we have studied analog figures of merit such as the transconductance ( ${g}_{m}$ ), output resistance ( ${r}_{o}$ ), transconductance generation factor ( ${g}_{m}/{I}_{D}$ ), and the intrinsic gain ( ${g}_{m}{r}_{o}$ ) for different molar fractions. Similarly, we have evaluated the RF performance of the SiNR and GNR TFETs as a function of cutoff frequency ( ${f}_{T}$ ), gate capacitance ( ${C}_{G}$ ), and transport delay ( $\tau$ ).

Asymmetric-Fluidic-Reservoirs Induced High Rectification Nanofluidic Diode

We demonstrate a novel nanofluidic diode that produces rectification factors in excess of 1000. The nanofluidic diode consists of ion permselective nanopores that connect two reservoirs of different diameters- a micropore reservoir and a macropore reservoir. On the application of +100 V to the micropore, a low OFF state current is observed. The OFF state is caused by formation of the ion depleted zone in the micropore because the anions are prevented from entering the nanopores from the micropore and the cations are depleted in this region to maintain charge neutrality. On the application of −100 V, we observe a high ON state current. The ON state is caused by formation of the ion enriched zone in the microchannel because the anions cannot pass through the nanopores and accumulate in the microchannel. To maintain charge neutrality the cations also become enriched in the microchannel. The ratio of ON state current to the OFF state current gives the rectification of current. Here, plasma oxidation is used to achieve a nanopore with a large wall surface charge density of σn = −55 mC/m2 which yields a rectification of current on the order of 3500 that is nearly two orders of magnitude higher than those reported thus far. In contrast to the other nanofluidic diodes, this nanofluidic diode does not introduce asymmetry to the nanopore, but asymmetry is produced by having the nanopores join a micropore and a macropore. Introduction of asymmetry into the fluidic reservoirs which the nanopores connect is quite simple. Hence, the nanofluidic diode is easy to scale up to industrial level.

Improving the Gate-Induced Drain Leakage and On-State Current of Fin-Like Thin Film Transistors with a Wide Drain

Polycrystalline silicon (poly-Si) thin film transistors (TFT) with a tri-gate fin-like structure and wide drain were designed and simulated to improve gate-induced drain leakage (GIDL), ON-state current, and breakdown voltage. The GIDL of fin-like TFTs (FinTFTs) examined in this study was dominated by longitudinal band-to-band tunneling (L-BTBT). Extending the wide drain can effectively suppress the longitudinal electric field near the drain and improve L-BTBT GIDL and breakdown. In addition, a wider drain can lead to a large cross section in the current path and improve the ON-state current. FinTFTs with wide drain exhibit a low GIDL, a high ON-state current, and high breakdown voltage, while maintaining favorable gate controllability.

Comparison of the performance improvement for the two novel SOI-tunnel FETs with the lateral dual-gate and triple-gate

In this paper, we present two silicon-on-insulator tunnel field-effect transistors (SOI-TFETs), referred as a lateral dual-gate TFET and a lateral triple-gate TFET, which consist of one or two vertical thin vertical dielectric layers within the original front-gate region and form the separate dual-gate or triple-gate structure. Using calibrated two-dimensional Synopsys Sentaurus TCAD simulation, we demonstrate that the proposed novel TFETs have relatively higher Ion and significantly lower Ioff due to the modulating effect of the multiple gate voltages on the channel barrier. We also compare and analyze improvements in Ion/Ioff for the two novel SOI-TFETs and a conventional SOI-TFET. The proposed new TFETs exhibit a high Ion/Ioff ratio of 104 ~ 108 for a channel length of 22 nm. Our results reveal that the performance of the lateral triple-gate TFET is superior to that of the dual-gate TFET, yielding higher on-state current and lower off-state current.

Low-Dispersion, High-Voltage, Low-Leakage GaN HEMTs on Native GaN Substrates

In this paper, the advantages of GaN high electron mobility transistors (HEMTs) grown on native GaN over GaN/Si or GaN/sapphire substrates are investigated and correlated with epitaxial material quality. Transmission electron microscopy plan-view and cross-sectional analyses of GaN/GaN reveal dislocation densities below ${1} \times {10}^{{6}}$ cm−2, which is at least three orders of magnitude lower than that of GaN/Si or GaN/sapphire. In the case of GaN/Si, the dislocations not only originate from the substrate/nucleation layer interface, but also the strain relief and isolation buffer stacks are main contributors to the dislocation density. GaN/GaN HEMTs show superior electrical and thermal performance and feature three orders of magnitude lower OFF-state leakage. The current collapse (also referred to as current dispersion or $R_{ \mathrm{\scriptscriptstyle ON}}$ -increase) after stress bias is less than 15% compared with 50% in the case of GaN/Si. A 2% drop of the ON-state current due to self-heating in dc operation when compared with 13% and 16% for GaN/Si and GaN/sapphire, respectively. The GaN/Si thermal performance becomes comparable to that of GaN/GaN only after substrate removal. Therefore, GaN/GaN provides high ON-state current, low OFF-state leakage current, minimal current collapse, and enhanced thermal power dissipation capability at the same time, which can directly be correlated with the absence of high dislocation density.

Enhanced photoresponsivity and hole mobility of MoTe2 phototransistors by using an Al2O3 high-κ gate dielectric

Molybdenum ditelluride (MoTe2) has been demonstrated great potential in electronic and optoelectronic applications. However, the reported effective hole mobility remains far below its theoretical value. Herein, taking advantage of high-κ screening effect, we have fabricated back-gated MoTe2 transistors on an Al2O3 high-κ dielectric and systematically investigated the electronic and optoelectronic properties. A high current on/off ratio exceeding 106 is achieved in the Al2O3-based MoTe2 transistors, and the hole mobility is demonstrated to be 150 cm2 V−1 s−1, compared to 0.2–20 cm2 V−1 s−1 ever obtained from back-gated MoTe2 transistors in the literatures. Moreover, a considerable hole concentration of 1.2 × 1013 cm−2 is attained in our Al2O3-based MoTe2 transistors owing to the strong gate control capability, leading to a high on-state hole current of 6.1 μA μm−1. After optimization, our Al2O3-based MoTe2 phototransistor exhibits outstanding photodetective performance, with a high responsivity of 543 A W−1 and a high photogain of 1,662 at 405 nm light illumination, which are boosted around 419 times compared to the referential SiO2-based control devices. The mechanisms of photoconductivity in the Al2O3-based MoTe2 phototransistors have been analyzed in detail, and the photogating effect is considered to play an important role. This work may provide useful insight to improve carrier mobility in two-dimensional layered semiconductors and open opportunities to facilitate the development of high-performance photodetectors in the future.

Analytical model of surface potential profiles and transfer characteristics for hetero stacked tunnel field-effect transistors

An analytical model of surface potential profiles and transfer characteristics for hetero stacked tunnel field-effect transistors (HS-TFETs) is presented for the first time, where hetero stacked materials are composed of two different bandgaps. The bandgap of the underlying layer is smaller than that of the upper layer. Under different device parameters (upper layer thickness, underlying layer thickness, and hetero stacked materials) and temperature, the validity of the model is demonstrated by the agreement of its results with the simulation results. Moreover, the results show that the HS-TFETs can obtain predominant performance with relatively slow changes of subthreshold swing (SS) over a wide drain current range, steep average subthreshold swing, high on-state current, and large on–off state current ratio.

Ferroelectric HfZrOx-based MoS2 negative capacitance transistor with ITO capping layers for steep-slope device application

A negative capacitance field-effect transistor (NCFET) built with hafnium-based oxide is one of the most promising candidates for low power-density devices due to the extremely steep subthreshold swing (SS) and high on-state current induced by incorporating the ferroelectric material in the gate stack. Here, we demonstrated a two-dimensional (2D) back-gate NCFET with the integration of ferroelectric HfZrOx in the gate stack and few-layer MoS2 as the channel. Instead of using the conventional TiN capping metal to form ferroelectricity in HfZrOx, the NCFET was fabricated on a thickness-optimized Al2O3/indium tin oxide (ITO)/HfZrOx/ITO/SiO2/Si stack, in which the two ITO layers sandwiching the HfZrOx film acted as the control back gate and ferroelectric gate, respectively. The thickness of each layer in the stack was engineered for distinguishable optical identification of the exfoliated 2D flakes on the surface. The NCFET exhibited small off-state current and steep switching behavior with minimum SS as low as 47 mV/dec. Such a steep-slope transistor is compatible with the standard CMOS fabrication process and is very attractive for 2D logic and sensor applications and future energy-efficient nanoelectronic devices with scaling power supply.

Full-quantum modeling of III-V Tunnel-FETs architectures

This paper review the device and circuit performance of co-optimized n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95Sb platform, using a full-quantum ballistic simulator. Based on 3D full-quantum simulations, the investigated devices feature steep subthreshold slopes and relatively high ON-state currents, and are combined to realize an inverter. Benchmarking against aggressively scaled CMOS logic based on multigate architectures highlights the potential of the proposed TFET implementations to perform up to 10× and 100× faster for IOFF = 5nA/um and 10 pA/um, respectively, at very low supply voltage VDD = 0.25V, for equal levels of static power dissipation. Afterwards, a simulation study on the impact of interface traps and strain on the I–V characteristics is carried out, in order to capture the effect of interface/border traps on the device electrostatics. The effect of an experimental Dit distribution of a high-k gate stack on InAs is investigated. Unfortunately, traps induce a significant reduction of the ON-state current. However, it turns out that localized strain at the source/channel heterojunction caused by lattice mismatch is able to induce a performance enhancement for the n-type TFET, with respect to the ideal device, even in the presence of traps. On the contrary, for the p-type one, a current degradation  18% is observed.

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported, to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The ION/IOFF of ISE-CGAA-SB-MOSFET increases by 1177 times and offers steeper subthreshold slope (~60 mV/decade). However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

Double-gate-all-around tunnel field-effect transistor**Project supported by the National Natural Science Foundation of China (Grant Nos. 61176038 and 61474093), the Science and Technology Planning Project of Guangdong Province, China (Grant No. 2015A010103002), and the Technology Development Program of Shanxi Province, China (Grant No. 2016GY075).

In this work, a double-gate-all-around tunneling field-effect transistor is proposed. The performance of the novel device is studied by numerical simulation. The results show that with a thinner body and an additional core gate, the novel device achieves a steeper subthreshold slope, less susceptibility to the short channel effect, higher on-state current, and larger on/off current ratio than the traditional gate-all-around tunneling field-effect transistor. The excellent performance makes the proposed structure more attractive to further dimension scaling.

Performance investigation of hetero material (InAs/Si)‐based charge plasma TFET

The charge plasma-based tunnel field-effect transistor (TFET) has been seen as the potential candidate to replace the conventional TFET as it offers fabrication simplicity and its proficiency to be used for ultra-low-power applications. A charge plasma TFET (CPTFET) with hetero materials for enhancement of device performance is presented. For this, a narrow bandgap material (InAs) is used instead of silicon in source region for reducing the lateral tunnelling distance at the source/channel interface. The reduced tunnelling width at the source/channel junction enables higher band-to-band tunnelling generation rate, thus the device offers higher ON-state current. In this context, a comparative study of CPTFET and hetero junction charge plasma TFET (H-CPTFET) has been performed in terms of transfer characteristic ( I ds - V gs ), transconductance ( g m ), gate-to-drain capacitance ( C gd ), cut-off frequency ( f T ) and gain-bandwidth product. In addition to this, the effect of variation in channel length ( L g ) and drain to source voltage ( V ds ) on the DC and analogue/radio frequency performance of H-CPTFET is also analysed.