High On-off Current Ratio Research Articles

고분자/무기 하이브리드 절연막을 이용한 용액공정용 저분자 박막트랜지스터의 안정성 향상 연구

Solution-processed small molecular semiconductors (soluble acenes) serve as ideal active materials for high-performance, printed organic thin-film transistors (OTFTs). However, device stability of soluble acene TFTs has not been intensively studied. Here, we showed that device stability of soluble acene TFTs can be significantly enhanced by the use of polymer/inorganic hybrid gate-dielectrics. Triethylsilylethynyl-anthradithiophene (TES-ADT) TFTs fabricated on polystyrene (PS)/ hybrid gate dielectrics exhibited high performance such as high field-effect mobility () and on-off current ratio (). In addition, transfer characteristic of the TFTs did not shift under the prolonged gate-bias (8000s). This outstanding device stability is due to the device structure which consists of highly crystalline TES-ADT crystals and trap-free PS/ dielectric.

A tunnel-induced injection field-effect transistor with steep subthreshold slope and high on-off current ratio

In this letter, a tunnel-induced injection field-effect transistor (TI-FET) is proposed and demonstrated. Compared with conventional tunneling field-effect transistor, by changing N-type drain into P-type and inserting a N-type pocket layer into the underlap region, off-state current is appreciably reduced, due to higher hole barrier induced by the inserted N-type pocket layer which can prevent hole leakage current from the drain. During the switching process, the gate controlled tunneling electrons from the source are trapped in the N-type pocket region and simultaneously decrease the hole barrier of the drain, which can increase hole injection current much more rapidly than the hole diffusing over a barrier directly controlled by a gate as in P-type metal-oxide-semiconductor field-effect transistor and thus ensure a very steep subthreshold slope. When the device is switched on, on-state current can be enhanced due to the dominant hole current diffusing from the drain, which is higher than pure tunneling current. Therefore, this TI-FET can obtain high on-current, low off-current, as well as steep subthreshold slope.

Graphene nanogap for gate-tunable quantum-coherent single-molecule electronics

We present atomistic calculations of quantum coherent electron transport through fulleropyrrolidine terminated molecules bridging a graphene nanogap. We predict that three difficult problems in molecular electronics with single molecules can be solved by utilizing graphene contacts: (1) a back gate modulating the Fermi level in the graphene leads facilitates control of the device conductance in a transistor effect with high on-off current ratio; (2) the size mismatch between leads and molecule is avoided, in contrast to the traditional metal contacts; (3) as a consequence, distinct features in charge flow patterns throughout the device are directly detectable by scanning techniques. We show that moderate graphene edge disorder is unimportant for the transistor function.

High-Performance Si Nanowire Transistors on Fully Si Bulk Substrate From Top-Down Approach: Simulation and Fabrication

A new method to fabricate high-performance gate-all-around silicon (Si) nanowire transistors (SNWTs) based on fully Si bulk (FSB) substrate is proposed and demonstrated by both simulation and experiments in this paper. Due to the large fan-out and deep junction of Si source/drain (S/D) region connecting with the bulk substrate, the FSB SNWTs can effectively alleviate the self-heating effects with technology scaling. Thermal behavior of multiwire SNWTs is investigated and FSB SNWTs show superior self-heating immunity to SNWTs based on Si-on-insulator (SOI) substrate (SOI SNWTs). In addition, the bottom parasitic transistor can be well suppressed in this structure. Although FSB SNWTs have larger gate parasitic capacitance, the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> is found to be comparable to the SOI SNWTs. With self-aligned, fully epi-free compatible CMOS processes, this new architecture was successfully fabricated, which exhibit high on-off current ratio of 2.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> due to better heat dissipation and low S/D resistance realized in this structure.

Photoconductive Properties of Selenium Nanowire Photodetectors

Selenium nanowires with a diameter of about 70 nm and a growth direction along [001] were fabricated via a facile solution method. Photoconductive properties of Se wires were systematically characterized via photodetectors made of single Se nanowire. The photodetectors exhibited a high light on-off current ratio (Ilight/ Idark) of 450, and a fast light response speed of millisecond rise/fall time with excellent stability and reproducibility. It was also observed that the response time strongly depend on the intensity of the illumination light: the rise time and fall time for a typical photodetector is 0.68/1.85, 0.53/1.70, 0.54/1.65, 0.51/1.59, and 0.49/1.58 ms for light intensity of 0.18, 0.26, 0.43, 0.96, and 1.89 mW/cm2, respectively, and the relationship between the light intensity and the photocurrent can be fitted by using a simple power law. The diameters of the nanowire were found to have a significant influence on the response speed with smaller Se nanowires showing higher response speed. Finally, the mechanisms of photoconduction and factors affecting the performance of the photodetectors were elucidated.

Low-voltage InGaZnO thin-film transistors with Al2O3 gate insulator grown by atomic layer deposition

We report on low-voltage, high-performance amorphous indium gallium zinc oxide n-channel thin-film transistors fabricated using 100-nm-thick Al2O3 grown by atomic layer deposition as the gate dielectric layer. The Al2O3 gate dielectric shows very small current densities and has a capacitance density of 81±1 nF/cm2. Due to a very small contact resistance, transistors with channel lengths ranging from 100 μm down to 5 μm yield a channel-independent, field-effect mobility of 8±1 cm2/V s, subthreshold slopes of 0.1±0.01 V/decade, low threshold voltages of 0.4±0.1 V, and high on-off current ratios up to 6×107 (W/L=400/5 μm) at 5 V.

The research on suspended ZnO nanowire field-effect transistor

This paper reports that a novel type of suspended ZnO nanowire field-effect transistors (FETs) were successfully fabricated using a photolithography process, and their electrical properties were characterized by I–V measurements. Single-crystalline ZnO nanowires were synthesized by a hydrothermal method, they were used as a suspended ZnO nanowire channel of back-gate field-effect transistors (FET). The fabricated suspended nanowire FETs showed a p-channel depletion mode, exhibited high on-off current ratio of ∼105. When VDS = 2.5 V, the peak transconductances of the suspended FETs were 0.396 μS, the oxide capacitance was found to be 1.547 fF, the pinch-off voltage VTH was about 0.6 V, the electron mobility was on average 50.17cm2/Vs. The resistivity of the ZnO nanowire channel was estimated to be 0.96 × 102 Ω cm at VGS = 0 V. These characteristics revealed that the suspended nanowire FET fabricated by the photolithography process had excellent performance. Better contacts between the ZnO nanowire and metal electrodes could be improved through annealing and metal deposition using a focused ion beam.

High-performance InGaZnO thin-film transistors with high-k amorphous Ba0.5Sr0.5TiO3 gate insulator

We report on high-performance n-channel thin-film transistors (TFTs) fabricated using amorphous indium gallium zinc oxide (a-IGZO) and amorphous Ba0.5Sr0.5TiO3 (a-BST) as the channel and gate dielectric layers, respectively. a-BST∕a-IGZO TFTs achieve low-voltage operation with a high saturation mobility value of 10±1cm2∕Vs, excellent subthreshold slopes of 0.06±0.01V/decade, a low threshold voltage of 0.5±0.1V, and a high on-off current ratio up to 8×107 (W∕L=1000μm∕5μm) at 3V. The high capacitance density of a-BST (145±2nF∕cm2) and the small contact resistance, smaller than the channel resistance, are responsible for the high performance of these TFTs.

Low-voltage high-performance C60 thin film transistors via low-surface-energy phosphonic acid monolayer/hafnium oxide hybrid dielectric

C 60 -based organic thin film transistors (OTFTs) have been fabricated using a n-octadecylphosphonic acid self-assembled monolayer/sol-gel processed hafnium oxide hybrid dielectric. With the combination of high capacitance (580 nF/cm2) and low leakage current density (8×10−9 A/cm2), this hybrid dielectric yields C60 OTFTs operating under 1.5 V with an average n-channel saturation field-effect mobility of 0.28 cm2/V s, high on-off current ratio of 105, and low subthreshold slope of 100 mV/decade. The low surface energy of the n-octadecylphosphonic acid allows C60 to form a thin film with large grains that provide an efficient charge carrier pathway for the low-voltage OTFTs.

Hexagonal a-Si:H TFTs: A New Advanced Technology for Flat-Panel Displays

Inverted stagger hexagonal hydrogenated amorphous silicon thin-film transistors (a-Si:H HEX-TFTs) were fabricated with a five-photomask process used in the processing of the active-matrix liquid crystal displays. We show that the output current of a-Si:H HEX-TFTs connected in parallel increases linearly with their number within a given pixel circuit. Current-voltage measurements indicate that a high ON-OFF current ratio and a low subthreshold slope can be maintained for multiple HEX-TFTs connected in parallel, whereas the field-effect mobility and threshold voltage remain identical to a single a-Si:H HEX-TFT. Due to a unique device geometry, an enhanced electrical stability and a larger pixel aperture ratio can be achieved in the multiple a-Si:H HEX-TFT in comparison to a standard single a-Si:H TFT having the same channel width. These HEX-TFT electrical characteristics are very desirable for active-matrix organic light-emitting displays.

P Channel Mosfet Devices in Nanocrystalline Silicon

AbstractWe report on the growth and properties of p-channel nanocrystalline Si thin film transistor (TFT) devices. In contrast to previous work, the devices are fabricated in n-body nanocrystalline Si. The doping of the n-body is systematically changed by doping with ppm levels of phosphorous. The threshold voltage was found to change systematically as phosphorus content increased. The TFT devices are of the bottom-gate type, grown on oxidized Si wafers. Source and drain contacts were provided by using either plasma grown p type nanocrystalline layers, or by the simple process of Al diffusion. A top layer of plasma-deposited silicon dioxide was found to decrease the off current significantly. High on-off current ratios exceeding 106 were obtained. Hole mobilities in the devices were consistently good, with the best mobility being in the range of ~1.3 cm2/V-s.

수소 플라즈마 처리를 이용한 역스테거드형 펜타센 트랜지스터의 전기적 특성 향상에 대한 연구

In order to reach the high electrical quality of organic thin film transistors (OTFTs) such as high mobility and on-off current ratio, it is strongly desirable to study the enhancement of electrical properties in OTFTs. Here, we report the novel method of hydrogen plasma treatment to improve electrical properties in inverted staggered OTFTs based on pentacene as active layer. To certify the effect of this method, we compared the electrical properties of normal device as a reference with those of device using the novel method. In result, the normal device as a reference making no use of this method exhibited a field effect mobility of 0.055 <TEX>$\textrm{cm}^2$</TEX>/Vs, on/off current ratio of 10<TEX>$^3$</TEX>, threshold voltage of -4.5 V, and subthreshold slope of 7.6 V/dec. While the device using the novel method exhibited a field effect mobility of 0.174 <TEX>$\textrm{cm}^2$</TEX>/Vs, on/off current ratio of 10<TEX>$\^$</TEX>6/, threshold voltage of -0.5 V, and subthreshold slope of 1.49 V/dec. According to these results, we have found the electrical performances in inverted staggered pentacene TFT owing to this method are remarkably enhanced. So, this method plays a key role in highly improving the electric performance of OTFTs. Moreover, this method is the first time yet reported for any OTFTs.

P‐8: Hydrogen Plasma Treatment on the Electrical Characterization of Inverted Staggered Pentacene Thin Film Transistors

AbstractIn order to reach the high electrical quality of organic thin film transistors OTFTs such as high mobility and on‐off current ratio, it is strongly desirable to study the enhancement of electrical properties in OTFTs. Here, we report the novel method of hydrogen plasma treatment to improve electrical properties in inverted staggered OTFTs based on pentacene as active layer. To certify the effect of this method, we compared the electrical properties of normal device as a reference with those of device using the novel method. In result, the normal device as a reference making no use of this method exhibited a field effect mobility of 0.055 2/Vs, on/off current ratio of 103, threshold voltage of −4.5 V, and subthreshold slope of 7.6 V/dec. While the device using the novel method exhibited a field effect mobility of 0.174 2/Vs, on/off current ratio of 106, threshold voltage of −0.5 V, and subthreshold slope of 1.49 V/dec. According to these results, we have found the electrical performances in inverted staggered pentacene TFT owing to this method are remarkably enhanced. So, this method plays a key role in highly improving the electric performance of OTFTs. Moreover, this method is the first time yet reported for any OTFTs.

Metal-induced laterally crystallized polycrystalline silicon for integrated sensor applications

A novel metal-induced lateral crystallization (MILC) technique, involving a low temperature crystallization step followed by a high temperature recrystallization step, has been applied to the formation of polycrystalline silicon (poly-Si) with enhanced material characteristics. A range of devices, including piezo-resistors, thermistors, resistors and thin-film transistors, has been fabricated both on MILC and regular low-pressure chemical vapor deposited (LPCVD) poly-Si. Compared to the latter, MILC poly-Si leads to much improved device performance. The piezo-resistive gauge factor of MILC poly-Si is at least double that of LPCVD poly-Si, with a maximum value of 60 measured, higher mobility, steeper subthreshold slope, lower threshold voltage, and higher on-off current ratio have been obtained for thin-film transistors realized on MILC poly-Si that those realized on LPCVD poly-Si. A variety of sensing and electronic devices based on MILC poly-Si can be simultaneously realized, thus making MILC an enabling technology for integrated silicon sensor applications.

A novel depletion-gate amorphous silicon thin-film transistor

A novel type of amorphous silicon (a-Si) thin-film transistor (TFT) in which a depletion gate is added to the top of the second nitride layer of a conventional a-Si TFT has been fabricated. In this transistor, switching is done by the depletion gate instead of the accumulation gate as in conventional a-Si TFTs. The pinch-off voltage and ON-OFF current ratio of the transistor can be changed by the accumulation gate bias. The transistor exhibits high ON-OFF current ratio, low contact resistance, and low gate-source capacitance. >

Novel two-step SDB technology for high-performance thin-film SOI/MOSFET applications

A novel two-step oxided silicon wafer direct bonding process (TSDB) for fabricating high-quality SOI substrates is presented, which has no contamination, no complex thinning process and no subsurface damage. The fracture strength of the SOI/TSDB material is 180 kg/cm2. SOI/TSDB NMOS and PMOS devices (0.8–3μm) have shown that the typical values of electron and hole surface channel mobility are 680 and 320cm2/Vs, respectively. A high device transconductance end high on-off current ratio have also been obtained.