High-level Parallel Research Articles

Optimized implementation of an improved KNN classification algorithm using Intel FPGA platform: Covid-19 case study

The improved k-nearest neighbor (KNN) algorithm based on class contribution and feature weighting (DCT-KNN) is a highly accurate approach. However, it requires complex computational steps which consumes much time for the classification process. A field programmable gate array (FPGA) can be used to solve this drawback. However, using traditional hardware description language (HDL) to implement FPGA-based accelerators requires a high design time. Fortunately, the open computing language (OpenCL) high level parallel programming tool allows rapid and effective design on FPGA-based hardware accelerators. In this study, OpenCL has been used to examine speeding up the DCT-KNN algorithm on the FPGA parallel computing platform through applying numerous parallelization and optimization techniques. The optimized approach of the improved KNN could be used in various engineering problems that require a high speed of classification process. Classification of the COVID-19 disease is the case study used to examine this work. The experimental results show that implementing the DCT-KNN algorithm on the FPGA platform (Intel De5a-net Arria-10 device was used) gives an extremely high performance when compared to the traditional single-core-CPU based implementation. The execution time for our optimized design on the FPGA accelerator is 44 times faster than the conventional design implemented on the regular CPU-based computational platform.

Simplified High Level Parallelism Expression on Heterogeneous Systems through Data Partition Pattern Description

Abstract With the development of heterogeneous systems, the demand for high-level programming methods that ease heterogeneous programming and produce portable applications has become more urgent. This paper proposes DACL, the data associated computing language. DACL introduces data partition patterns to achieve architecture-independent parallelism expression. Meanwhile, DACL provides simplified language extensions, as well as programming features such as serialization of the computing process, parameterization of data attributes and modularity, thus reducing the difficulty of heterogeneous programming and improving programming productivity. The operational semantics show that DACL enables different levels of parallelism degree calculation and retains data access patterns, reserving optimization potential. To support cross-platform execution, the currently implemented source-to-source compilers employ OpenMP and OpenCL as the backend. We reconstructed multiple benchmarks selected from the Parboil and Rodinia benchmark suits with DACL and conducted a comparison test on CPU, GPU and MIC platforms. The code size of each rebuilt benchmark is roughly equivalent to that of the serial code, which is only 13%–64% of the benchmark OpenCL code. With the support of the compilation system, the reconstructed code can execute on different processors without modification, yielding a competitive or better performance to that of the manually written benchmark code.

SparseP

Several manufacturers have already started to commercialize near-bank Processing-In-Memory (PIM) architectures, after decades of research efforts. Near-bank PIM architectures place simple cores close to DRAM banks. Recent research demonstrates that they can yield significant performance and energy improvements in parallel applications by alleviating data access costs. Real PIM systems can provide high levels of parallelism, large aggregate memory bandwidth and low memory access latency, thereby being a good fit to accelerate the Sparse Matrix Vector Multiplication (SpMV) kernel. SpMV has been characterized as one of the most significant and thoroughly studied scientific computation kernels. It is primarily a memory-bound kernel with intensive memory accesses due its algorithmic nature, the compressed matrix format used, and the sparsity patterns of the input matrices given. This paper provides the first comprehensive analysis of SpMV on a real-world PIM architecture, and presents SparseP, the first SpMV library for real PIM architectures. We make three key contributions. First, we implement a wide variety of software strategies on SpMV for a multithreaded PIM core, including (1) various compressed matrix formats, (2) load balancing schemes across parallel threads and (3) synchronization approaches, and characterize the computational limits of a single multithreaded PIM core. Second, we design various load balancing schemes across multiple PIM cores, and two types of data partitioning techniques to execute SpMV on thousands of PIM cores: (1) 1D-partitioned kernels to perform the complete SpMV computation only using PIM cores, and (2) 2D-partitioned kernels to strive a balance between computation and data transfer costs to PIM-enabled memory. Third, we compare SpMV execution on a real-world PIM system with 2528 PIM cores to an Intel Xeon CPU and an NVIDIA Tesla V100 GPU to study the performance and energy efficiency of various devices, i.e., both memory-centric PIM systems and conventional processor-centric CPU/GPU systems, for the SpMV kernel. SparseP software package provides 25 SpMV kernels for real PIM systems supporting the four most widely used compressed matrix formats, i.e., CSR, COO, BCSR and BCOO, and a wide range of data types. SparseP is publicly and freely available at https://github.com/CMU-SAFARI/SparseP. Our extensive evaluation using 26 matrices with various sparsity patterns provides new insights and recommendations for software designers and hardware architects to efficiently accelerate the SpMV kernel on real PIM systems.

A cross-platform OpenVX library for FPGA accelerators

FPGAs are an excellent platform to implement computer vision applications, since these applications tend to offer a high level of parallelism with many data-independent operations. However, the freedom in the solution design space of FPGAs represents a problem because each solution must be individually designed, verified, and tuned. The emergence of High Level Synthesis (HLS) helps solving this problem and has allowed the implementation of open programming standards as OpenVX for computer vision applications on FPGAs, such as the HiFlipVX library developed exclusively for Xilinx devices. Although with the HiFlipVX library, designers can develop solutions efficiently on Xilinx, they do not have an approach to port and run their code on FPGAs from other manufacturers. This work extends the HiFlipVX capabilities in two significant ways: supporting Intel FPGA devices and enabling execution on discrete FPGA accelerators. To provide both without affecting user-facing code, the new carried out implementation combines two HLS programming models: C++, using Intel’s system of tasks, and OpenCL, which provides the CPU interoperability. Comparing with pure OpenCL implementations, this work reduces kernel dispatch resources, saving up to 24% of ALUT resources for each kernel in a graph, and improves performance 2.6 × and energy consumption 1.6 × on average for a set of representative applications, compared with state-of-the-art frameworks.

Light-stimulated artificial photonic synapses based on solution-processed In-Sn-Zn-O transistors for neuromorphic applications

Artificial photonic synapse devices (PSDs) hold great promise for the realization of next-generation artificial vision systems and processing units through a synergistic combination of brain-inspired neuromorphic computing and high levels of parallelism. Here, we demonstrate artificial PSDs based on solution-processed In-Sn-Zn-O (indium-tin-zinc oxide, ITZO) thin films capable of mimicking various neuromorphic functions. In particular, a transistor structure was adopted for PSDs to enable a facile control of the photo-response characteristics by gate biasing. With optimized gate bias condition, enhanced electrical conductance modulation was possible which can improve the energy efficiency of PSDs. In addition, we investigated the dependency of photo-response characteristics on light pulse waveforms to find out the correlation between various pulse parameters and the photo-current generation. Based on these findings, we demonstrated the emulation of associative learning which is one of the important cognitive functions of the brain. Moreover, to verify the translation of optically derived synaptic behaviors of ITZO PSDs into artificial neuromorphic computing, pattern recognition of handwritten digit patterns was demonstrated showing an accuracy up to 90.3%.

Fast and Effective Retrieval for Large Multimedia Collections

The indexing and retrieval of multimedia content is generally implemented by employing feature graphs. These graphs typically contain a significant number of nodes and edges to reflect the level of detail in feature detection. A higher level of detail increases the effectiveness of the results, but also leads to more complex graph structures. However, graph traversal-based algorithms for similarity are quite inefficient and computationally expensive, especially for large data structures. To deliver fast and effective retrieval especially for large multimedia collections and multimedia big data, an efficient similarity algorithm for large graphs in particular is desirable. Hence, in this paper, we define a graph projection into a 2D space (Graph Code) and the corresponding algorithms for indexing and retrieval. We show that calculations in this space can be performed more efficiently than graph traversals due to the simpler processing model and the high level of parallelization. As a consequence, we demonstrate experimentally that the effectiveness of retrieval also increases substantially, as the Graph Code facilitates more levels of detail in feature fusion. These levels of detail also support an increased trust prediction, particularly for fused social media content. In our mathematical model, we define a metric triple for the Graph Code, which also enhances the ranked result representations. Thus, Graph Codes provide a significant increase in efficiency and effectiveness, especially for multimedia indexing and retrieval, and can be applied to images, videos, text and social media information.

Exploiting Machine Learning For Improving In-Memory Execution of Data-Intensive Workflows on Parallel Machines

Workflows are largely used to orchestrate complex sets of operations required to handle and process huge amounts of data. Parallel processing is often vital to reduce execution time when complex data-intensive workflows must be run efficiently, and at the same time, in-memory processing can bring important benefits to accelerate execution. However, optimization techniques are necessary to fully exploit in-memory processing, avoiding performance drops due to memory saturation events. This paper proposed a novel solution, called the Intelligent In-memory Workflow Manager (IIWM), for optimizing the in-memory execution of data-intensive workflows on parallel machines. IIWM is based on two complementary strategies: (1) a machine learning strategy for predicting the memory occupancy and execution time of workflow tasks; (2) a scheduling strategy that allocates tasks to a computing node, taking into account the (predicted) memory occupancy and execution time of each task and the memory available on that node. The effectiveness of the machine learning-based predictor and the scheduling strategy were demonstrated experimentally using as a testbed, Spark, a high-performance Big Data processing framework that exploits in-memory computing to speed up the execution of large-scale applications. In particular, two synthetic workflows were prepared for testing the robustness of the IIWM in scenarios characterized by a high level of parallelism and a limited amount of memory reserved for execution. Furthermore, a real data analysis workflow was used as a case study, for better assessing the benefits of the proposed approach. Thanks to high accuracy in predicting resources used at runtime, the IIWM was able to avoid disk writes caused by memory saturation, outperforming a traditional strategy in which only dependencies among tasks are taken into account. Specifically, the IIWM achieved up to a 31% and a 40% reduction of makespan and a performance improvement up to 1.45× and 1.66× on the synthetic workflows and the real case study, respectively.

A fast and quantitative measurement of shear wave speed and attenuation using (cross) modal assurance criterion for acoustic radiation force elasticity imaging

The measurement of shear wave speed (SWS) or attenuation in soft materials, especially in biological tissues, plays a crucial role in acoustic radiation force elasticity imaging which provides a quantitative measurement of elastic properties. In this study, with the first attempt to apply modal analysis theory to acoustic radiation force elasticity imaging, we propose a fast tracking algorithm based on the modal assurance criterion (MAC) including 2D SWS-MAC for SWS measurement and the signed cross modal assurance criterion (CrossMAC) for shear wave attenuation measurement. These approaches achieved high speedup with a framework of high-level parallelism. The FEM simulation results proved the accuracy of these two approaches. Phantom experiments showed that the 2D SWS-MAC approach had good consistency in SWS estimation compared to existing approaches and could accurately preserve the boundary contour of the inclusion with narrowed assurance intervals (quarter-width assurance intervals). An excised porcine liver experiment verified the effectiveness of shear wave attenuation estimation with Signed CrossMAC. These results demonstrate that the MAC based approaches improved both the shear wave motion measurement precision and the speedup rate of the measurement compared to conventional time domain cross-correlation or time-to-peak methods.

Energy and performance improvements in stencil computations on multi-node HPC systems with different network and communication topologies

Energy and performance improvements in stencil computations are relevant for both application developers and data center administrators. They appear as the fundamental scheme in many large-scale scientific simulations and workloads. Many research efforts have focused on some estimation techniques of the energy usage of HPC systems based on specific characteristics of parallel applications. In case of stencils, we have previously concentrated on detailed estimations of energy consumption and the energy-aware distribution of stencil computations on heterogeneous processors. However, we have restricted our comprehensive studies to a single heterogeneous computing node only. In this paper, we show how scheduling and optimization techniques can be applied for energy and performance improvements of stencil computations on multi-node HPC systems using different network topologies. We formulate a scheduling model together with a new Tabu Search algorithm, called Task Movement (TM), taking into account the communication hierarchies, to minimize the overall energy usage and the execution time of stencil computations. Experimental studies show that this algorithm solves the considered problem more efficiently comparing to other, simpler heuristics. We present computational experiments for a reference 7 point stencil computation pattern on three commonly used low-diameter network topologies: Fat-tree, Dragonfly, and Torus. According to our studies, the most promising multi-node HPC architecture for stencil computations is based on the Torus network concept. Finally, we argue that the proposed scheduling model and TM algorithm can be easily adopted within existing high-level parallel execution environments for stencils automatic performance tuning.

Systolic architecture for adaptive block FIR filter for throughput using distributed arithmetic

In this paper, the design of distributed arithmetic (DA) finite impulse response (FIR) filter using block least mean square algorithm (BLMS) based on systolic array architecture with parallel data processing units is presented. A high level of parallelism is observed in the proposed work, improving the efficiency of variable coefficient FIR structure. The parallel look-up tables (LUT) in combination with the shift accumulator emulate multiply and accumulate operations. In order to reduce the number of clock cycles, B parallel LUTs are used, where B is the coefficient size. The block processing in BLMS Adaptive FIR Filter of block length L gives L times high throughput. This structure accepts block of input samples and generates block of output in each clock cycle. It requires less number of registers for computing filter output response and weight increment vector as memory reuse concept is used for implementing registers. This structure doesn’t require multiplexer. The designed DA based FIR filter is implemented on FPGA. The implementation results shows that the manuscript presents a high speed and low power architecture. The proposed structure provides 17.3 times less power and 9.5 times increase in throughput when compared to existing designs.

Identifying insufficient data coverage in databases with multiple relations

In today's data-driven world, it is critical that we use appropriate datasets for analysis and decision-making. Datasets could be biased because they reflect existing inequalities in the world, due to the data scientists' biased world view, or due to the data scientists' limited control over the data collection process. For these reasons, it is important to ensure adequate data coverage across different groups over the intersection of multiple attributes. Often, the dataset to be analyzed is obtained through complex joins and predicate combinations over multiple relational tables in a database. Due to the sheer data volume we often have to deal with, determining adequate coverage can require an unacceptably long execution time. In this paper, we provide an efficient approach for coverage analysis, given a set of attributes across multiple tables. To identify regions with insufficient coverage in the combinatorially large set of value combinations, we design an index scheme to avoid explicit table joins, achieve efficient memory usage, and support predicate combination at a high level of parallelism. We also propose P-WALK , a priority-based search algorithm, to traverse the lattice space. Since in practice, coverage assessment typically does not require precise COUNT aggregation results, we further present approximate methods to reduce computation time. Experimental evaluation using three real-world datasets shows the effectiveness, efficiency, and accuracy of proposed methods.

Guest Editor’s Note: High-Level Parallel Programming 2019

Guest Editor’s Note: High-Level Parallel Programming 2019

Comparison of Baseband Processors in Terms of Realization SDR-Transceivers

Software-defined Radio is a programmable transceiver with the capability of operating various wireless communication protocols without the need to change or update the hardware. Consequently, Software-defined Radio has earned a lot of attention and is of great significance to both academia, military and aerospace industry. Components of Software-defined Radio (e.g. mixers, filters, amplifiers, modulators/demodulators, detectors, etc.) implemented by means of software on a personal computer or embedded system. Operation of signal processing are handed over to the baseband processor, rather than being done in special electronic circuits. Baseband processors are implemented through employing various types of hardware platforms, such as General Purpose Processors, Graphics Processing Units, Digital Signal Processors, and Field Programmable Gate Arrays. Each of these platforms is associated with their own set of advantages and disadvantages. In this paper was proposed a comparison of the state-of-the-art hardware platforms in the context of implementation Software-defined Radio transceivers. For comparison was determined as follow criteria: computational power of hardware platform, power consumption, complexity of developing, and cost of tools and equipment. First approaches to realizing baseband processors is using a General Purpose Processor and accelerating by Graphics Processing Units. But General Purpose Processor and Graphics Processing Units execute software instructions in the sequential order. For this reason, General Purpose Processors are not convenient for high-throughput computing with real-time requirements. Also this hardware platforms have increased power consumption. This aspect does not allow use General Purpose Processor and Graphics Processing Units in small and portable Software-defined Radio transceivers. In other hand, General Purpose Processors are preferable hardware platform by researchers and beginners due to their flexibility and programmability. Therefore, General Purpose Processors and Graphics Processing Units is highly recommended for prototyping Software-defined Radio platforms. Digital Signal Processor was reviewed as alternative approach for implementing baseband processors. Digital Signal Processors is a particular type of General Purpose Processors that is optimized to process digital signals. Digital Signal Processors have similar disadvantage with insufficient computational power, but some manufacturer sell energy optimized Digital Signal Processors. Consequently, Digital Signal Processor is commonly used in small and portable Software-defined Radio transceivers. Field Programmable Gate Arrays and System-on-Chips with Field Programmable Gate Array are strongly recommended for high-performance Software-defined Radio platforms. This hardware platforms combine the flexibility of processors and efficiency of small Digital Signal Processor. Field Programmable Gate Arrays can achieve a high level of parallelism in executing digital signal processing. However, the designers must have a high degree in digital electronics and good acknowledgement of hardware description languages. After the research, was proposed own flexible architecture Software-defined Radio transceiver and methods for development.

Design of a real-time face detection architecture for heterogeneous systems-on-chips

Object detection represents one of the most important and challenging task in computer vision applications. Boosting-based approaches deal with computational intensive operations and they involve several sequential tasks that make very difficult developing hardware implementations with high parallelism level. This work presents a new hardware architecture able to perform object detection based on a cascade classifier in real-time and resource-constrained systems. As case study, the proposed architecture has been tailored to accomplish the face detection task and integrated within a complete heterogeneous embedded system based on a Xilinx Zynq-7000 FPGA-based System-on-Chip. Experimental results show that, thanks to the proposed parallel processing scheme and the runtime adaptable strategy to slide sub-windows across the input image, the novel design achieves a frame rate up to 125fps for the QVGA resolution, thus significantly outperforming previous works. Such a performance is obtained by using less than 10% of on-chip available logic resources with a power consumption of 377 mW at the 100 MHz clock frequency.

Faster RooFitting: Automated parallel calculation of collaborative statistical models

RooFit [1,2] is the main statistical modeling and fitting package used to extract physical parameters from reduced particle collision data, e.g. the Higgs boson experiments at the LHC [3,4]. RooFit aims to separate particle physics model building and fitting (the users’ goals) from their technical implementation and optimization in the back-end. In this paper, we outline our efforts to further optimize this back-end by automatically running parts of user models in parallel on multi-core machines. A major challenge is that RooFit allows users to define many different types of models, with different types of computational bottlenecks. Our automatic parallelization framework must then be flexible, while still reducing run-time by at least an order of magnitude, preferably more. We have performed extensive benchmarks and identified at least three bottlenecks that will benefit from parallelization. We designed a parallelization layer that allows us to parallelize existing classes with minimal effort, but with high performance and retaining as much of the existing class’s interface as possible. The high-level parallelization model is a task-stealing approach. Preliminary results show speed-ups of factor 2 to 20, depending on the exact model and parallelization strategy.

Efficient scheduling of streams on GPGPUs

Graphics processing units (GPUs) are widely used for scientific and engineering applications with high level of parallelism. The computing power of GPUs is improving through enhancing their architectural facilities. NVIDIA’s compute unified device architecture (CUDA) stream using hyper-Q on NVIDIA graphic cards is a reputable capability for performance improvement. Without any synchronization and based on architectural capabilities, NVIDIA’s CUDA stream allows some processes to run simultaneously. Experimental results show that how to stream a number of programs affect the execution time. Therefore, the stream set with the highest amount of performance improvement is the efficient stream set. This article proposes a framework to predict the efficient stream set on two streams without trying all combinations, which would be a very time-consuming process. The proposed framework employs a performance model and a scheduler. The performance model estimates the duration of simultaneous portions of streamed programs and the scheduler uses the estimation of the model to predict the efficient stream set. The proposed prediction method relies on non-stream features of programs. The results show that even with 33% error of performance model in average, the scheduler predicts the optimized sets with 100% precision.

VLSI implementation of distributed arithmetic based block adaptive finite impulse response filter

In this paper, an efficient VLSI architecture of distributed arithmetic (DA) based block least mean square (BLMS) adaptive finite impulse response (ADFIR) filter implementation with parallel processing is proposed. In DA scheme, the filter partial products are precomputed and saved in lookup table (LUT) and then by using shift and accumulation operations filtering can be done. To improve the efficiency, a high level of parallelism is incorporated in the design of variable coefficient ADFIR filter. The parallel LUT followed by shift-accumulate operations replaces multiply and accumulate (MAC) operations. By using BLMS algorithm in ADFIR filter with block length P gives P times fast throughput. Since memory reuse concept is used, the design requires less number of registers to calculate output vector and coefficient increment vector. The proposed design is implemented on FPGA. The implementation results indicate that the proposed design is a low power and high speed architecture. The proposed structure provides 47.4% less power and 22.7% less delay when compared to existing designs.

Upgrade of the KEDR detector DAQ system

The KEDR experiment is ongoing at the VEPP-4M e+e− collider at Budker INP in Novosibirsk. The collider center of mass energy range covers a wide spectrum from 2 to 11 GeV. Most of the up-to-date statistics were taken at the lower end of the energy range around the charmonia region. Planned activities at greater energies up to the bottomonia would lead to a significant increase of event recording rates and accelerator backgrounds, thus stressing the existing DAQ and trigger systems beyond their limits. The described DAQ upgrade plan includes: the redesign of the trigger electronics using modern components to improve the trigger decision time; the development of new readout processors using ethernet connections; new software for collecting events and electronics management; high level of parallelization of data transfers and events processing; improved reliability based on readout computing cluster with redundancy. The upgraded DAQ system is going to be very flexible and could be considered as a concept prototype of the projected BINP Super Charm-Tau Factory.

Unique Sense: A Smart Computing Prototype 3

Technological development and growth create demands on various computing solutions for diversified problems across all the domains. Research initiation project named Unique sense intense to find an alternate frugal computing solution to satisfy the computing demands in emerging technology which can adopt for different eco system. This research work is continuity of unique sense proto type 1 and unique sense prototype 2 for investigate the possibility of deliverance and compatibility to deal the big data problem along with Fault tolerance and reliable process and to deliver solution to the next phase of prolonging GPU supporting kits with RISC computing architecture for various computing requirements and real-time needs. It is capable to deliver provisions for high level data management and parallel processing. The smart features and capacity of multi-level parallel working enables customization of mechanism dynamically, environment friendly and also reusable for next generation demands.

Energy-Efficient and Quality-Assured Approximate Computing Framework Using a Co-Training Method

Approximate computing is a promising design paradigm that introduces a new dimension—error—into the original design space. By allowing the inexact computation in error-tolerance applications, approximate computing can gain both performance and energy efficiency. A neural network (NN) is a universal approximator in theory and possesses a high level of parallelism. The emerging deep neural network accelerators deployed with NN-based approximator is thereby a promising candidate for approximate computing. Nevertheless, the approximation result must satisfy the users’ requirement, and the approximation result varies across different applications. We normally deploy an NN-based classifier to ensure the approximation quality. Only the inputs predicted to meet the quality requirement can be executed by the approximator. The potential of these two NNs, however, is fully explored; the involving of two NNs in approximate computing imposes critical optimization questions, such as two NNs’ distinct views of the input data space, how to train the two correlated NNs, and what are their topologies. In this article, we propose a novel NN-based approximate computing framework with quality insurance. We advocate a co-training approach that trains the classifier and the approximator alternately to maximize the agreement of the two NNs on the input space. In each iteration, we coordinate the training of the two NNs with a judicious selection of training data. Next, we explore different selection policies and propose to select training data from multiple iterations, which can enhance the invocation of the approximate accelerator. In addition, we optimize the classifier by integrating a dynamic threshold tuning algorithm to improve the invocation of the approximate accelerator further. The increased invocation of accelerator leads to higher energy efficiency under the same quality requirement. We propose two efficient algorithms to explore the smallest topology of the NN-based approximator and the classifier to achieve the quality requirement. The first algorithm straightforward searches the minimum topology using a greedy strategy. However, the first algorithm incurs too much training overhead. To solve this issue, the second one gradually grows the topology of NNs to match the quality requirement by transferring the learned parameters. Experimental results show significant improvement on the quality and the energy efficiency compared to the existing NN-based approximate computing frameworks.