High-level Synthesis Techniques Research Articles

Microarchitectural synthesis of performance-constrained, low-power VLSI designs

New portable signal-processing applications such as mobile telephony, wireless computing, and personal digital assistants place stringent power consumption limits on their constituent components. Substantial power savings can be realized if 5 V designs are translated to use the new lower supply voltage standards. This conversion, however, is not achieved easily: a design originally targeted for implementation in a 5 V technology will typically require significant rework to meet timing and throughput requirements at the lower operating voltage. In this paper we describe a high-level synthesis system which assists the designer in performing this task, minimizing the need for manual redesign. Techniques employed in this work include pipelining and a new approach to module selection that minimizes power consumption subject to timing constraints. Using these and other high-level synthesis techniques to target designs to 3.3 V libraries, we show that it is possible to reduce power consumption by as much as 56% as compared to the original 5 V implementation, while meeting specified minimum throughput and maximum latency constraints.

Influence of high-level synthesis on average and peak temperatures of CMOS circuits

The aim of this paper is introducing a new modified high-level synthesis (HLS) technique resulting in reduction of the power dissipation in CMOS circuits leading to lowering the peak and the average temperature of the designed chip. The presented approach enables us designing contemporary electronic systems with reduction of the peak and average power consumption, so the reliability of the system can be improved. In the present method, the initial HLS is performed by the ASAP algorithm [The Synthesis Approach to Digital System Design, 1992]. In the next stage, acceptable increase of the toggling time of chosen functional units (without exceeding the system throughput — the latency is constant) leads to the possibility of decreasing their supply voltages. These chosen functional units are determined by the inserting idle operations with interchanging (IIOI) algorithm. This approach leads to decreasing the power dissipated in the chosen functional units and finally their peak and average temperature is lowered.

A review of high-level synthesis for dynamically reconfigurable FPGAs

Dynamically Reconfigurable Field Programmable Gate Arrays (DR FPGAs) change many of the basic assumptions of what hardware is. DR FPGA-based dynamically reconfigurable computing has become a powerful methodology for achieving high performance while minimizing the resource required in the implementation of many applications. The key to harnessing the power of DR FPGAs for most applications is to develop high-level synthesis tools for transforming automatically an algorithmic level behavioral specification into DR FPGA configurations. In this paper we survey the current state-of-the-art in high-level synthesis techniques for dynamically reconfigurable systems. The differences in high-level synthesis technology between classical systems and dynamically reconfigurable systems are discussed. Then, we describe the basic tasks in the high-level synthesis of dynamically reconfigurable systems. Finally, techniques that have been developed in the past few years for the high-level synthesis of dynamically reconfigurable systems are presented.

High-level address optimization and synthesis techniques for data-transfer-intensive applications

Data-transfer intensive applications typically contain heavily accessed memories involving considerable arithmetic for the computation and the selection of the different memory access pointers. This data processing, namely addressing, becomes dominant in the overall arithmetic cost and it has to be executed under very tight timing constraints. Different high-level optimizing alternatives suitable for addressing are explored in our Adopt methodology and prototype tool environment to reduce the addressing overhead. They include address expression splitting/clustering, induction variable analysis, target architecture selection, and global-scope algebraic optimization. In addition, some steps aiming to reduce at the system level the time-multiplexed address unit cost, are also incorporated for area and power efficiency. The techniques are demonstrated on test-vehicles representative of real-life applications, shelving important savings on the overall arithmetic cost.

High-level synthesis techniques for functional test pattern execution

Functional debugging often dominates the time and cost of the ASIC system development, mainly due to the limited controllability and observability of the storage elements in designs, and therefore the intermediate variables in functional specifications. We propose a new divide-and-conquer approach for maximizing the simultaneous controllability of an arbitrary set of the user-selected variables in the design at the debugging time for facilitating the functional test pattern execution while minimizing the hardware overhead. The approach imposes minimal restriction on register sharing so that the synthesized designs will have the desired characteristic while minimizing the additional hardware overhead and minimizing the disruption of the optimization potential when scheduling, allocation and binding tasks in high-level synthesis are performed. The effectiveness of the proposed approach is demonstrated on a number of designs.

Automatic generation of reprogrammable microcoded controllers within a high-level synthesis environment

Existing techniques in high-level synthesis mostly assume a simple controller model in the form of a single FSM. In reality more complex controller architectures are often used. On the other hand, in the case of programmable processors the controller architecture is largely defined by the available control-flow instructions in the instruction set. With the wider acceptance of behavioural synthesis, the application of these methods for the design of programmable controllers is of fundamental importance in embedded system technology. An important extension of an existing architectural synthesis system targeting the generation of reprogrammable microcoded controllers is described. The designer can then generate both styles of architecture, hardwired and programmable, using the same synthesis system and can quickly evaluate the trade-offs of hardware decisions.

Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system

As high-level synthesis techniques gain acceptance among designers, it is important to be able to provide a robust system which can handle large designs in short execution times, producing high-quality results. Scheduling is one of the most complex tasks in high-level synthesis, and although many algorithms exist for solving the scheduling problem, it remains a main source of inefficiency by either not producing high-quality results, not taking into account realistic design requirements, or requiring unacceptable execution times. One of the main problems in scheduling is the dichotomy between control and data. Many algorithms to date have been able to provide scheduling solutions by looking only at either the data part or the control part of the design. This has been done in order to simplify the problem; however, it has resulted in many algorithms unable to handle efficiently large designs with complex control and data functionality. This paper presents algorithms for combining dataflow and control-flow techniques into a robust scheduling system. The main characteristics of this system are as follows: 1) it uses path-based techniques for efficient handling of control and mutual exclusiveness (for resource sharing), 2) it allows operation reordering and parallelism extraction within the context of path-based scheduling, 3) it contains a control partitioning algorithm for design space exploration as well as for reducing the number of control paths, and 4) it combines the above algorithms into an adaptive scheduling system which is capable of trading optimality for execution time on-the-fly. Results involving billions of paths are presented and analyzed.

High-level synthesis in an industrial environment

The use of modern hardware-description languages in the chip design process has allowed designs to be modeled at higher abstraction levels. More powerful modeling styles, such as register-transfer and behavioral level specifications, have spurred the development of high-level synthesis techniques in both industry and academia. However, despite the many research efforts, the technology is not yet in widespread use in industry. This paper presents the IBM High-Level Synthesis System (HIS), which is the first such system to be used in production in IBM. HIS synthesizes gate-level networks from VHDL models at various levels of abstraction. The main algorithms, modeling capabilities, and methodology considerations in the HIS system are presented. Results show that HIS is capable of producing implementations comparable to or better than those of the existing methodology, while shortening the design time significantly. The HIS system is currently in production use and evaluation in several IBM sites for processors and peripheral chip designs, as well as being an external commercial product.

Program implementation schemes for hardware-software systems

Recent advances in the design and synthesis of integrated circuits have prompted system architects to investigate computer aided design methods for systems that contain both application-specific and predesigned reprogrammable components. For the most part, we can apply high level synthesis techniques to synthesis of systems containing processors by treating the latter as a generalized resource. However, the problem is more complex, since the software on the processor implements system functionality in an instruction-driven manner with a statically allocated memory space, whereas ASICs operate as data driven reactive elements. Due to these differences in computational models and primitive operations in hardware and software, a new formulation of the problem of cosynthesis is needed. The authors present their cosynthesis approach. They specify system behavior using HardwareC, a hardware description language (HDL) that has a C-like syntax and supports timing and resource constraints. It also supports specification of unbounded and unknown delay operations that can arise from data-dependent decisions and external synchronization operations. The particular choice of a HDL to specify system functionality is immaterial for the cosynthesis formulation here, and other HDLs such as Verilog could be used.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Extending CAD tools and techniques

The possibility of supporting codesign with CAD tools is examined. It is argued that, since high-level synthesis techniques support the design of hardware from behavioral descriptions, whose abstractions are similar to those used in software programs, design tools may soon be able to handle some aspects of the concurrent design of hardware and software modules. The use of CAD tools in designing embedded systems and application-specific integrated circuits (ASICs), the benefits of mixed hardware-software systems, and open issues relating to CAD tools for codesign are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>