High-level Synthesis Approach Research Articles

Bio-mimicking DNA fingerprint profiling for HLS watermarking to counter hardware IP piracy

The multifaceted, multivendor-based global design supply chain induces hardware threats of intellectual property (IP) piracy for modern computing and electronic systems. Current hardware watermarking techniques fall short either in terms of watermark strength (size of covert constraints generated) or number of security layers/variables involved in the security constraints generation process. This paper presents a novel approach for high level synthesis (HLS) watermarking by bio-mimicking DNA fingerprint profiling to counter hardware IP piracy. The proposed approach effectively captures the vital DNA fingerprint profiling phases such as DNA sequencing, DNA fragmentation, fragment replication, DNA ligase, etc. and bio-mimics them to generate a digital watermarking framework. The presented approach has been demonstrated on convolutional layer and JPEG compression-decompression (CODEC) algorithms that are widely used in several medical and machine learning applications. The proposed approach has been thoroughly compared with several state-of-the-art approaches. The proposed approach depicts superior security in the probability of coincidence of up to ~ 104 and tamper tolerance of up to ~ 10368 at 0% overhead as compared to the prior approaches.

Notification Oriented Paradigm to Digital Hardware — A benchmark evaluation with Random Forest algorithm

The Notification Oriented Paradigm (NOP) emerges as an alternative to develop and execute applications. The NOP brings a new inference concept based on precise notifying collaborative minimal entities. This inference implicitly allows achieving decoupled solutions, thereby enabling parallelism at a granularity level as fine-grained as possible in the envisaged computational platform. Previous research has proposed a digital circuit solution based on the NOP model, which is called NOP to Digital Hardware (DH), as a sort of High-Level Synthesis (HLS) prototype tool. The results with NOP-DH were encouraging indeed. However, the previous NOP-DH works lack benchmarks that exploit well-known algorithms against known HLS tools, such as the Vivado HLS tool, which is one of the suitable commercial HLS solutions. This work proposes evaluating the NOP-DH applied to develop the well-known Random Forest algorithm. The Random Forest is a popular Machine Learning algorithm used in several classification and regression applications. Due to the high number of logic-causal evaluations in the Random Forest algorithm and the possibility of running them in parallel, it is suitable for envisaged benchmark purpose. Experiments were performed to compare NOP-DH, and two Vivado HLS approaches (an ad hoc code and a hls4ml tool-based code) in terms of performance, amount of logic elements, maximum frequency, and the number of predictions per second. Those experiments demonstrated that NOP-DH circuits achieve better results concerning the number of logical elements and prediction rates, with some scalability limitations as a drawback. On average, the NOP-DH uses 52.5% fewer resources, and the number of predictions per second is 4.7 times higher than Vivado HLS. Finally, our codes are made publicly available at https://nop.dainf.ct.utfpr.edu.br/nop-public/nop-dh-random-forest-algorithm.

Generating circuits with generators

The most widely used languages and methods used for designing digital hardware fall into two rough categories. One of them, register transfer level (RTL), requires specifying each and every component in the designed circuit. This gives the designer full control, but burdens the designer with many trivial details. The other, the high-level synthesis (HLS) method, allows the designer to abstract the details of hardware away and focus on the problem being solved. This method however cannot be used for a class of hardware design problems because the circuit's clock is also abstracted away. We present YieldFSM, a hardware description language that uses the generator abstraction to represent clock-level timing in a digital circuit. It represents a middle ground between the RTL and HLS approaches: the abstraction level is higher than in RTL, but thanks to explicit information about clock-level timing, it can be used in applications where RTL is traditionally used. We also present the YieldFSM compiler, which uses methods developed by the functional programming community -- including continuation-passsing style translation and defunctionalization -- to translate YieldFSM programs to Mealy machines. It is implemented using Template Haskell and the Clash functional hardware description language. We show that this approach leads to short and conceptually simple hardware descriptions.

N-PIR: A Neighborhood-Based Pareto Iterative Refinement Approach for High-Level Synthesis

N-PIR: A Neighborhood-Based Pareto Iterative Refinement Approach for High-Level Synthesis

Signature based Merkle Hash Multiplication algorithm to secure the communication in IoT devices

Great extent of modernization in intelligent device automation and wireless sensor network have encouraged the augmentation of IoTs to interconnect millions of actual devices to the Internet with the help of sensors, actuators and communication technologies. IoT devices with the potential of pervasive sensing and quantifying ability, it becomes an essential segment of the future Internet. The sixth generation (6G) enabled IoT networks are predicted to transform the data sharing and communication for a future of thorough brilliant and sovereign systems. However, secure communication in a sensor network is very difficult and is more amplified by the use of latest 6G IoT technology which is vulnerable to different kinds of attacks due to their limited security features. Existing security systems like RSA and Elliptic curve cryptography which is based on large integer factors and the discrete logarithmic problem is vulnerable to the attack which emerges from quantum computers. The computing capacity of a quantum computer is higher than classical computers. A 30-qubit quantum computer has the equivalent computing capacity as a traditional silicon-based computer computes at 10 teraflops per second. To secure the communication in the present and future IoT network, an enhanced Hash-based Post-Quantum Cryptography (PQC) architecture named Signature-based Merkle Hash Multiplication (SMHM) algorithm is proposed. In the proposed scheme, the Hash-based Merkle signature algorithm is enhanced using the Bernoulli Karatsuba Multiplication algorithm to secure the data storage and communication in IoT devices. The FPGA based proposed model is implemented in the Xilinx ISE14.5 simulator, both Hardware Descriptive Language (HDL) and High-Level Synthesis (HLS) approach is used to calculate the performance metrics which improved 33% frequency, 22% area, power consumption up to 13%, 10% error and 15% delay.

From C/C++ Code to High-Performance Dataflow Circuits

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where performance is limited by long latency control decisions. In this work, we describe an HLS approach which generates dynamically scheduled, dataflow circuits out of imperative code. We detail a complete set of rules to transform a standard compiler intermediate representation into a high-performance dataflow circuit that is able to dynamically resolve memory dependences and adapt its behavior on the fly to particular control flow decisions and operation latencies. Compared to a traditional HLS tool, the result is a different tradeoff between performance and circuit complexity: statically scheduled circuits display the best performance per cost in regular applications, but general-purpose, irregular, and control-dominated computing tasks require the runtime flexibility of dynamic scheduling. Therefore, enabling dynamic behavior in HLS is key to dealing with the increasing computational demands of new contexts and broader application domains.

A high-level synthesis approach for precisely-timed, energy-efficient embedded systems

Embedded systems continue to rapidly proliferate in diverse fields, including medical devices, autonomous vehicles, and more generally, the Internet of Things (IoT). Many embedded systems require application-specific hardware components to meet precise timing requirements within limited resource (area and energy) constraints. High-level synthesis (HLS) is an increasingly popular approach for improving the productivity of designing hardware and reducing the time/cost by using high-level languages to specify computational functionality and automatically generate hardware implementations. However, current HLS methods provide limited or no support to incorporate or utilize precise timing specifications within the synthesis and optimization process. In this paper, we present a hybrid high-level synthesis (H-HLS) framework that integrates state-based high-level synthesis (SB-HLS) with performance-driven high-level synthesis (PD-HLS) methods to enable the design and optimization of application-specific embedded systems in which timing information is explicitly and precisely defined in state-based system models. We demonstrate the results achieved by this H-HLS approach using case studies including a wearable pregnancy monitoring device, an ECG-based biometric authentication system, and a synthetic system, and compare the design space exploration results using two PD-HLS tools to show how H-HLS can provide low energy and area under timing constraints. © 2021 Elsevier Science. All rights reserved

Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis

Field-Programmable Gate Arrays (FPGA) are often present in energy-efficient systems, although its non-trivial development flow is an obstacle for massive adoption. High-Level Synthesis (HLS) approaches attempt to mitigate the gap by targetting FPGAs from software languages, however manual tuning is still essential to meet performance demands. We present a high-level design space exploration framework with timing and resource awareness that uses an estimator named Lina to evaluate each design point. Lina is a profiling-based approach that avoids the costly static analyses performed by HLS compilers, allowing a significantly faster exploration of optimisations. Estimations are improved by supporting a continuous range of operating frequencies and by considering resource usage for both floating-point and integer datapaths. For a given set of C kernels, the estimated solutions are among the best 1% for execution time and resource footprint. The exploration of each kernel using Lina was performed on average two orders of magnitude faster than using early HLS compiler reports, and four orders of magnitude faster than fully compiling each design point. By considering the design spaces traversed, our solutions reached 70% of the maximum speed-up achievable. This represents an average speed-up of 14-16× compared to the baseline designs with no optimisations enabled.

Q-PIR: A quantile based Pareto iterative refinement approach for high-level synthesis

High level synthesis (HLS) tools enable the use of high level languages such as C, C++ and SystemC for VLSI design. This simplifies the programming task and also allows the programmers to apply various pragmas or synthesis directives for controlling the hardware design parameters. Since these directives can take multiple values and also can be applied in many places for ASIC and FPGA designs, the design space grows exponentially making the design space exploration time consuming. Predicting Pareto optimal designs by performing HLS for minimum possible designs has been a driving force to bring in the learning techniques such as Random forests and Gaussian Process models. However, these techniques suffer from scalability issues in large design space or are ineffective in utilizing the prediction uncertainty information for model refinement. We propose a novel active learning approach for design space exploration (Q-PIR) based on the theory of Quantile Regression Forests. Our technique uses the conditional quantiles and prediction intervals to build the region of prediction uncertainty for model refinement and Pareto front discovery in the objective space of area and latency. Through experimental evidence across HLS specific benchmarks, our approach demonstrates better performance in Pareto front discovery than the state-of-the art approaches.

Real-Time FPGA Accelerated Stereo Matching for Temporal Statistical Pattern Projector Systems.

The presented paper describes a hardware-accelerated field programmable gate array (FPGA)–based solution capable of real-time stereo matching for temporal statistical pattern projector systems. Modern 3D measurement systems have seen an increased use of temporal statistical pattern projectors as their active illumination source. The use of temporal statistical patterns in stereo vision systems includes the advantage of not requiring information about pattern characteristics, enabling a simplified projector design. Stereo-matching algorithms used in such systems rely on the locally unique temporal changes in brightness to establish a pixel correspondence between the stereo image pair. Finding the temporal correspondence between individual pixels in temporal image pairs is computationally expensive, requiring GPU-based solutions to achieve real-time calculation. By leveraging a high-level synthesis approach, matching cost simplification, and FPGA-specific design optimizations, an energy-efficient, high throughput stereo-matching solution was developed. The design is capable of calculating disparity images on a 1024 × 1024(@291 FPS) input image pair stream at 8.1 W on an embedded FPGA platform (ZC706). Several different design configurations were tested, evaluating device utilization, throughput, power consumption, and performance-per-watt. The average performance-per-watt of the FPGA solution was two times higher than in a GPU-based solution.

Recommender system implementations for embedded collaborative filtering applications

This paper starts proposing a complete recommender system implemented on reconfigurable hardware with the purpose of testing on-chip, low-energy embedded collaborative filtering applications. Although the computing time is lower than the one obtained from usual multicore microprocessors, this proposal has the advantage of providing an approach to solve any prediction problem based on collaborative filtering by using an off-line, highly-portable light computing environment. This approach has been successfully tested with state-of-the-art datasets. Next, as a result of improving certain tasks related to the on-chip recommender system, we propose a custom, fine-grained parallel circuit for quick matrix multiplication with floating-point numbers. This circuit was designed to accelerate the predictions from the model obtained by the recommender system, and tested with two small datasets for experimental purposes. The accelerator is built from two levels of parallelism. On the one hand, several predictions run in parallel through the simultaneous multiplication of different vectors of two matrices. On the other hand, the operation of each vector is executed in parallel by multiplying pairs of floating-point values to later add the corresponding results in parallel as well. This circuit was compared with other approaches designed for the same purpose: circuits built using automatized tools of high-level synthesis, a general-purpose microprocessor, and high-performance graphical processing units. The performance of the prediction accelerator in terms of time surpassed that of the other approaches. We also evaluated the scalability of the circuit to practical problems using the high-level synthesis approach, and confirmed that implementations based on reconfigurable hardware allow acceptable speedups of multi-core processors.

Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets

High Level Synthesis (HLS) tools targeting Field Programmable Gate Arrays (FPGAs) aim to provide a method for programming these devices via high-level abstractions. Initially, HLS support for FPGAs focused on compiling C/C++ to hardware circuits. This raised the issue of determining the programming practices which resulted in the best performing circuits. Recently, to further increase the applicability of HLS approaches, renewed effort was placed on support for HLS of OpenCL code for FPGA, raising the same issues of coding practices and performance portability. This paper explores the performance of OpenCL code compiled for FPGAs for different coding techniques. We evaluate the use of task-kernels versus NDRange kernels, data vectorization, the use of on-chip local memories, and data transfer optimizations by exploiting burst access inference. We present this exploration via a case study of the k-means algorithm, and produce a total of 10 OpenCL implementations of the kernel. To determine the effects of different data set characteristics, and to determine the gains from specialization based on number of attributes, we generated a total of 12 integer data sets. The data sets vary regarding the number of instances, number of attributes (i.e., features), and number of clusters. We also vary the number of processing cores, and present the resulting required resources and operating frequencies. Finally, we execute the same OpenCL code on a 4 GHz Intel i7-6700K CPU, showing that the FPGA achieves speedups up to $1.54 {\times } $ for four cases, and energy savings up to 80% in all cases.

Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL

Field-Programmable Gate Arrays (FPGAs) are widely used in the central signal processing design of the Square Kilometer Array (SKA) as hardware accelerators. The frequency domain acceleration search (FDAS) module is an important part of the SKA1-MID pulsar search engine. To develop for a yet to be finalized hardware, for cross-discipline interoperability and to achieve fast prototyping, OpenCL as a high-level FPGA synthesis approaches employed to create the sub-modules of FDAS. The FT convolution and the harmonic-summing plus some other minor sub-modules are elements in the FDAS module that have been well-optimized separately before. In this paper, we explore the design space of combining well-optimized designs, dealing with the ensuing need to trade-off and compromise. Pipeline computing is employed to handle multiple input arrays at high speed. The hardware target is to employ multiple high-end FPGAs to process the combined FDAS module. The results show interesting consequences, where the best individual solutions are not necessarily the best solutions for the speed of a pipeline where FPGA resources and memory bandwidth need to be shared. By proposing multiple buffering techniques to the pipeline, the combined FDAS module can achieve up to 2[Formula: see text] speedup over implementations without pipeline computing. We perform an extensive experimental evaluation on multiple high-end FPGA cards hosted in a workstation and compare to a technology comparable mid-range GPU.

SoC implementation of a photovoltaic reconfiguration algorithm by exploiting a HLS-based architecture

The dynamic reconfiguration of photovoltaic arrays is a promising technique for reducing the power drops due to partial shadowing. Some approaches for determining the optimal electrical configuration of the photovoltaic array have been presented in literature. The most encouraging solution is based on the use of stochastic algorithms that can be fruitfully implemented in a system on chip. The computation time takes profit from the available field programmable gate array fabric, where multiple instances of the fitness function can be run in parallel. The use of Vivado High Level Synthesis, to create a Register Transfer Level implementation from C/C++ sources, allows achieving satisfactory results. Coding the algorithm by taking into account the synthesis process, thus resource allocation, scheduling and binding, helps in obtaining a further performance improvement. In this paper a High Level Synthesis approach is used for the systematic exploration of the possible architectures that can be used for implementing the reconfiguration algorithm. Some solutions that differ in terms of computation time and hardware resources used are compared. The target system on chip is a low cost one from Xilinx.

A Multi-Layer Hardware Trojan Protection Framework for IoT Chips

Since integrated circuits are performed by several untrusted manufacturers, malicious circuits (hardware Trojans) can be implanted in any stage of the Internet-of-Things (IoT) devices. With the globalization of the IoT device manufacturing technologies, protecting the system-on-chip (SoC) security is always the keys issue for scientists and IC manufacturers. The existing SoC high-level synthesis approaches cannot guarantee both register-transfer-level and gate-level security, such as some formal verification and circuit characteristic analysis technologies. Based on the structural characteristics of hardware Trojans, we propose a multi-layer hardware Trojan protection framework for the Internet-of-Things perception layer called RG-Secure , which combines the third-party intellectual property trusted design strategy with the scan-chain netlist feature analysis technology. Especially at the gate level of chip design, our RG-Secure is equipped with a distributed, lightweight gradient lifting algorithm called lightGBM. The algorithm can quickly process high-dimensional circuit feature information and effectively improve the detection efficiency of hardware Trojans. In the meanwhile, a common evaluation index F-measure is used to prove the effectiveness of our method. The experiments show that RG-Secure framework can simultaneously detect register-transfer-level and gate-level hardware Trojans. For the trust-HUB benchmarks, the optimized lightGBM classifier achieves up to 100% true positive rate and 94% true negative rate; furthermore, it achieves 99.8% average F-measure and 99% accuracy, which shows a promising approach to ensure security during the design stage.

HLS Based Approach to Develop an Implementable HDR Algorithm

Hardware suitability of an algorithm can only be verified when the algorithm is actually implemented in the hardware. By hardware, we indicate system on chip (SoC) where both processor and field-programmable gate array (FPGA) are available. Our goal is to develop a simple algorithm that can be implemented on hardware where high-level synthesis (HLS) will reduce the tiresome work of manual hardware description language (HDL) optimization. We propose an algorithm to achieve high dynamic range (HDR) image from a single low dynamic range (LDR) image. We use highlight removal technique for this purpose. Our target is to develop parameter free simple algorithm that can be easily implemented on hardware. For this purpose, we use statistical information of the image. While software development is verified with state of the art, the HLS approach confirms that the proposed algorithm is implementable to hardware. The performance of the algorithm is measured using four no-reference metrics. According to the measurement of the structural similarity (SSIM) index metric and peak signal-to-noise ratio (PSNR), hardware simulated output is at least 98.87 percent and 39.90 dB similar to the software simulated output. Our approach is novel and effective in the development of hardware implementable HDR algorithm from a single LDR image using the HLS tool.

Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach

The original version of the article unfortunately contained error in author group. Four authors were not submitted and published in the original version.

An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters

This paper evaluates the benefits of using a high-level synthesis (HLS) tool to develop field-programmable gate array (FPGA)-based real-time simulators for power electronics systems. The investigated workflow generates a synthesizable hardware description from a system level C-code along with a set of directives that specify performance criteria such as area utilization and timing closure requirements. The performance of the HLS approach is evaluated for different circuit sizes and target clock frequencies. Results show that HLS can be used for hardware-in-the-loop (HIL) applications when the circuit to be simulated is small and the target clock frequency is not too high (up to 100 MHz). For larger circuits and higher clock frequencies, HLS will either require a simulation time-step that is too large for real-time simulation purposes, or will tend to use almost all of the FPGA resources.

TTHLS: an HLS tool for testable hardware generation

This paper presents a new methodology to incorporate testability to Technology driven high-level synthesis, which is a customized high level synthesis approach based on the target technology. This new methodology called testable technology driven high-level synthesis, generates testable hardware from the corresponding HDL input. Testability incorporation at this higher abstraction, using this integrated approach, proves to be better in terms of area and power consumption than the conventional approaches. The experimental results for the examples considered here prove that the proposed method can reduce up to 9.38% in terms of silicon area and 1.89% in terms of power consumption.

Efficient Memory Partitioning for Parallel Data Access in FPGA via Data Reuse

Parallelizing the memory accesses in a nested loop is a critical challenge to facilitate loop pipelining. An effective approach for high-level synthesis on field-programmable gate array is to map these accesses to multiple on-chip memory banks using a memory partitioning technique. In this paper, we propose an efficient memory partitioning algorithm with low overhead and low time complexity for parallel data access via data reuse. We find that for most applications in image and video processing, a large amount of data can be reused among different iterations of a loop nest. Motivated by this observation, we propose to cache reusable data using on-chip registers, organized as register chains. The nonreusable data are then separated into several memory banks by a memory partitioning algorithm. We revise the existing padding method to cover cases occurring frequently in our method wherein certain components of partition vector are zeros. Experimental results have demonstrated that compared with the state-of-the-art algorithms, the proposed method is efficient in terms of execution time, resource overhead, and power consumption across a wide range of access patterns extracted from applications in image and video processing. As for the testing patterns, the execution time is typically less than one millisecond. And the number of required memory banks is reduced by 59.7% on average, which leads to an average reduction of 78.2% in look-up tables, 65.5% in flip-flops, 37.1% in DSP48Es, and therefore 74.8% reduction in dynamic power consumption. Moreover, the storage overhead incurred by the proposed method is zero for most widely used access patterns in image filtering.