Abstract
High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where performance is limited by long latency control decisions. In this work, we describe an HLS approach which generates dynamically scheduled, dataflow circuits out of imperative code. We detail a complete set of rules to transform a standard compiler intermediate representation into a high-performance dataflow circuit that is able to dynamically resolve memory dependences and adapt its behavior on the fly to particular control flow decisions and operation latencies. Compared to a traditional HLS tool, the result is a different tradeoff between performance and circuit complexity: statically scheduled circuits display the best performance per cost in regular applications, but general-purpose, irregular, and control-dominated computing tasks require the runtime flexibility of dynamic scheduling. Therefore, enabling dynamic behavior in HLS is key to dealing with the increasing computational demands of new contexts and broader application domains.
Highlights
The use of FPGAs in datacenters by Microsoft [46], [10] and Amazon [2] as well as the acquisition of Altera by Intel [14] signal one of the greatest opportunities for FPGAs since they were first introduced
An alternative High-Level Synthesis (HLS) approach is to implement dynamic scheduling, where decisions on when each operation should execute are made in the circuit during runtime, achieving behaviors which are beyond the capabilities of statically scheduled circuits: apart from the ability to extract more parallelism when control and memory dependences are undecidable at compile time, dynamic scheduling helps to alleviate the need for complex loop transformation and the related programmer hints
The potentials of gain in terms of clock cycles saved in situations such as the one in this example are at least qualitatively clear, dynamic scheduling costs resources and time. To evaluate these area-performance tradeoffs, we compare our circuits with those obtained using a state-of-the-art HLS tool and we show that dynamic scheduling can reap significant performance benefits in appropriate situations
Summary
The use of FPGAs in datacenters by Microsoft [46], [10] and Amazon [2] as well as the acquisition of Altera by Intel [14] signal one of the greatest opportunities for FPGAs since they were first introduced. While there is conspicuous research activity on this front, HLS tools almost universally rely on building datapaths that are controlled following static schedules—that is, the cycle when every operation is executed is fixed at synthesis-time [19] This approach serves well applications that are fairly regular, it tends to produce conservative and low-performance results in irregular and general-purpose code, limiting the usability of HLS only to particular market segments. Beyond the scope of this paper, dynamic scheduling opens the door to speculative execution [35], one of the most powerful ideas in computer architecture These opportunities to exploit parallelism while minimizing the programming effort may be critical for FPGAs to compete with modern CPUs and, to deal with the increasing computational demands of the 21st century. In addition to our previously published work [34], this article discusses several new aspects of the Cto-dataflow conversion (e.g., ensuring deterministic behavior) and details all concepts which are incorporated into our complete and open-source HLS framework [36]
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
