High Lateral Electric Field Research Articles

An SOI-Based Lock-in Pixel with a Shallow Buried Channel for Reducing Parasitic Light Sensitivity and Improving Modulation Contrast

This paper presents a high-NIR sensitivity SOI-gate lock-in pixel with improved modulation contrast. The proposed pixel has a shallow buried channel and intermediate gates to create both a high lateral electric field and a potential barrier to parasitic light sensitivity. Device simulation results showed that parasitic light sensitivity reduced from 13.7% to 0.13% compared to the previous structure.

(Invited) Visualization of Charge Density Distribution in Parallel-Plate Dielectric Barrier Discharge Under Atmospheric-Pressure Air

Dielectric barrier discharge (DBD) is one of the atmospheric nonequilibrium plasma and is typically driven by sinusoidal or pulse voltage with electrodes that dielectric is inserted. DBD has been used in some industries such as plasma medicine and material processing. However, the fundamental process of DBD has not been elucidated yet. When a parallel plate DBD is driven by sinusoidal voltage under atmospheric pressure, numerous filamentary discharges called microdischarges (MDs) are observed. The surface charge deposited on the dielectric after the discharge plays a major role in the behavior of these MDs. As the MD develops during the gap and reaches the dielectric surface, a surface discharge occurs and deposits the charge on the dielectric surface.We performed dielectric surface charge measurements using Bi4Ge3O12, a Pockels crystal, in a short-gap, parallel-plate DBD of 0.5 and 0.3 mm driven by a sinusoidal high voltage. The high-speed camera enabled measurement of the spatio-temporal distribution of surface charge and estimation of the net electric field and the characteristics of microdischarges (MDs).The net electric field strength in the gap was estimated from the measurement results. The axial reduced electric field strength generated by the surface charge was found to be equivalent to 50-60% of the peak value of the applied electric field with all the voltage amplitude and gap length in this study, and the gap electric field after discharge was suppressed to less than 100 Td. Such a strong field keeps the MDs in a nonequilibrium plasma and also prevents re-discharge in the same position at the half cycle. On the other hand, the lateral electric field strength generated by the surface charge is largely characterized by the charge distribution—i.e., the voltage amplitude, gap length, and charge polarity—as mentioned above. Higher amplitude of applied voltage leads to an increase in the area of high lateral electric field strength above 100 Td. Compared to the gap length of 0.5 mm, the lateral electric field weakened, while the axial electric field generated by the surface charge was stronger in the gap length of 0.3 mm. As for the relationship between the charge polarity and the lateral electric field, the lateral field at the anodic dielectric, which the negative charge is deposited on, is dominant in the region of less than 100 Td. Meanwhile, on the cathodic dielectric, which the positive charge is deposited on, the area of above 100 Td is larger. That is, the strong lateral electric field can be observed near the cathodic dielectric, rather than the anodic dielectric. Thus, different chemical reactions may occur in the vicinity of the anodic and cathodic dielectrics, respectively, because of the difference in the drifting charged particles and the lateral field strength.

Exploiting Within-Channel Tunneling in a Nanoscale Tunnel Field-Effect Transistor

In this paper, using device simulations, we investigate electrical characteristics of a tunnel field-effect transistor (TFET) in which band-to-band tunneling (BTBT) occurs dominantly within the channel, rather than at source-channel junction. The within-channel BTBT is enabled by sharp band-bending induced by the dual material gate (DMG). The work-functions of two metal gates are chosen, such that the surface potential profile exhibits a distinct step at the DMG interface. Consequently, even under equilibrium condition, a high lateral electric field and an abrupt tunneling junction exist at the DMG interface. When a small gate voltage is applied, the inherent lateral electric field aids in creating an abrupt band alignment and obtaining a small tunneling width. As a result, an excellent average subthreshold swing is obtained in the proposed device. We have also investigated scaling of channel lengths in the proposed device and have demonstrated that within-channel tunneling can be exploited for channel lengths of 40nm and above. Furthermore, low drain threshold voltage and suppressed drain-induced barrier lowering can be obtained in the proposed device. Moreover, in contrast to conventional TFETs, electrical characteristics of the proposed device are less susceptible to source doping variations and shift in gate-edge with respect to the source-channel junction.

Effect of Oxygen Content on Current Stress-Induced Instability in Bottom-Gate Amorphous InGaZnO Thin-Film Transistors.

The effect of oxygen content on current-stress-induced instability was investigated in bottom-gate amorphous InGaZnO (a-IGZO) thin-film transistors. The observed positive threshold voltage shift (ΔVT) was dominated by electron trapping in the gate insulator (GI), whereas it was compensated by donor creation in a-IGZO active regions when both current flows and a high lateral electric field were present. Stress-induced ΔVT increased with increasing oxygen content irrespective of the type of stress because oxygen content influenced GI quality, i.e., higher density of GI electron traps, as well as typical direct current (DC) performance like threshold voltage, mobility, and subthreshold swing. It was also found that self-heating became another important mechanism, especially when the vertical electric field and channel current were the same, independent of the oxygen content. The increased ΔVT with oxygen content under positive gate bias stress, positive gate and drain bias stress, and target current stress was consistently explained by considering a combination of the density of GI electron traps, electric field relaxation, and self-heating-assisted electron trapping.

Comprehensive study of variability in poly-Si channel nanowire transistor

Variability in poly-Si nanowire transistors (NW Tr.) is studied with respect to device and grain size. Threshold voltage (Vth) variability decreases as grain size or NW width (W) decreases since the number of grain boundaries in carrier passage increases. Drain current (Id) variability shows similar grain size and W dependences, while Id variability in short channel Tr. is suppressed due to the parasitic resistance. In addition, Id variability decreases with high lateral or perpendicular electric field as well as high temperature due to potential barrier lowering at grain boundaries.

Dependence of Sub-Thermionic Swing on Channel Thickness and Drain Bias of Poly-Si Junctionless Thin-Film Transistor

We demonstrate the polycrystalline-silicon (poly-Si) junctionless (JL) thin-film transistor (TFT) with a planar structure and an ultra-thin channel film thickness ~1.5-nm exhibiting subthreshold swing (S.S.) less than 60 mV/decade. The S.S. of the poly-Si JL-TFT shows abnormal drain-voltage dependence, which the higher drain voltage leads to the smaller S.S. The minimum S.S. (S.S.min) observed in this letter is about 30 mV/decade, which is a record low S.S.min. The sub-60-mV/decade S.S. of the poly-Si JL-TFT is attributed to the impact ionization effect resulting from the high lateral electric field at the drain side at OFF-state. It is different from the conventional inversion-mode transistor, whose pinch-off point is observed at ON-state rather than the OFF-state. The lateral electric field is also found to be increasing with decreasing the channel thickness, and as a consequence, the impact ionization effect is more pronounced when the channel thickness is thinner. This letter shows a new concept for JL transistors, which would be helpful for the development of poly-Si JL-TFTs and the applications of 3-D integrated circuit and non-volatile memory.

Two-Dimensional Thickness-Dependent Avalanche Breakdown Phenomena in MoS2 Field-Effect Transistors under High Electric Fields.

As two-dimensional (2D) transition metal dichalcogenides electronic devices are scaled down to the sub-micrometer regime, the active layers of these materials are exposed to high lateral electric fields, resulting in electrical breakdown. In this regard, understanding the intrinsic nature in layer-stacked 2D semiconducting materials under high lateral electric fields is necessary for the reliable applications of their field-effect transistors. Here, we explore the electrical breakdown phenomena originating from avalanche multiplication in MoS2 field-effect transistors with different layer thicknesses and channel lengths. Modulating the band structure and bandgap energy in MoS2 allows the avalanche multiplication to be controlled by adjusting the number of stacking layers. This phenomenon could be observed in transition metal dichalcogenide semiconducting systems due to its quantum confinement effect on the band structure. The relationship between the critical electric field for avalanche breakdown and bandgap energy is well fitted to a power law curve in both monolayer and multilayer MoS2.

Microscopic electronic and structural analysis of femtosecond laser sulfur hyperdoped silicon

AbstractSulfur hyperdoping by fs laser irradiation is a promising process for improving absorption properties of crystalline silicon which indicates its suitability for manufacturing intermediate band silicon solar cells. Here, first results of a novel approach to study the electrical and structural properties of sulfur hyperdoped regions of p‐type silicon substrates are presented. In addition to electron beam induced current (EBIC) and transmission electron microscopy (TEM) in cross‐section geometry, shallow‐angle bevel polishing is used to employ surface sensitive techniques, such as atomic force microscopy (AFM) and Kelvin force microscopy (KFM). The latter reveals high lateral electric fields in regions beneath the crests of the surface topography, while EBIC shows an enhanced recombination activity at the location of the voltage drops. Both these effects are related to extended defects revealed by TEM and a possible lateral variation of sulfur concentrations.AFM image (top) and KFM map (bottom) showing a voltage drop on the surface of a terrace produced by bevel polishing of sulfur hyperdoped silicon.

A Stimulated Raman Scattering CMOS Pixel Using a High-Speed Charge Modulator and Lock-in Amplifier.

A complementary metal-oxide semiconductor (CMOS) lock-in pixel to observe stimulated Raman scattering (SRS) using a high speed lateral electric field modulator (LEFM) for photo-generated charges and in-pixel readout circuits is presented. An effective SRS signal generated after the SRS process is very small and needs to be extracted from an extremely large offset due to a probing laser signal. In order to suppress the offset components while amplifying high-frequency modulated small SRS signal components, the lock-in pixel uses a high-speed LEFM for demodulating the SRS signal, resistor-capacitor low-pass filter (RC-LPF) and switched-capacitor (SC) integrator with a fully CMOS differential amplifier. AC (modulated) components remained in the RC-LPF outputs are eliminated by the phase-adjusted sampling with the SC integrator and the demodulated DC (unmodulated) components due to the SRS signal are integrated over many samples in the SC integrator. In order to suppress further the residual offset and the low frequency noise (1/f noise) components, a double modulation technique is introduced in the SRS signal measurements, where the phase of high-frequency modulated laser beam before irradiation of a specimen is modulated at an intermediate frequency and the demodulation is done at the lock-in pixel output. A prototype chip for characterizing the SRS lock-in pixel is implemented and a successful operation is demonstrated. The reduction effects of residual offset and 1/f noise components are confirmed by the measurements. A ratio of the detected small SRS to offset a signal of less than 10−5 is experimentally demonstrated, and the SRS spectrum of a Benzonitrile sample is successfully observed.

Interband and intraband radiation from the n-InGaAs/GaAs heterostructures with quantum wells under the conditions of injection in high lateral electric fields

The interband and intraband radiation from the n-InGaAs/GaAs heterostructures with the double and triple tunnel coupled and selectively doped quantum wells (QWs), which is appeared under the lateral electric field and in the presence of hole injection from the anode contact, has been investigated. A steep increase of the interband radiation intensity was found at the fields of E≥1.7kV/cm. This effect should be related to the big lifetime of the injected charge carriers (~10−6s) which exceeds by three orders of magnitude the lifetime in the similar bulk direct-band semiconductor. Its reason lies in spatial separation of the injected holes and electrons between coupled wells, firstly, by the built-in transverse electric field between wells and, secondly, due to the real-space transfer of carriers heated by the lateral electric field from the wide well to the narrow δ-doped one. Furthermore, an increase of the carrier concentration due to injection leads to an increase of that transition intensity and, consequently, to an intensity increase of the radiative intersubband transitions of carriers in QWs which results in a steep intensity increase of the far (50–120µm) infrared radiation.

Direct Characterization of Impact Ionization Current in Silicon-on-Insulator Body-Contacted MOSFETs

Impact Ionization (I.I.) is an inherent phenomenon of very scaled MOSFET devices operated at a high lateral electric field regime (VD=VDD ). From the Silicon-On-Insulator prospective, it leads, not only to possible reliability issues arisen from the hot carrier generation, but also to the accumulation of charge in the body of the transistor [1]. This particularity yields a set of effects that depending on the application may be desirable or not; among them: kink effect, body-to-source junction forward biasing or bipolar triggering [3]. The use of body-contacted devices has allowed us the direct monitoring of the Impact Ionization phenomenon in two sets Silicon-On-Insulator transistors: Devices with silicon film thickness TSi=7nm and Buried Oxide Thickness of TBOX=145nm, and devices with TSi=26nm and TBOX=10nm. Both of them fabricated in a 22nm process at CEA-LETI facilities. Two types of measurements have been conducted by applying different contour conditions to the body-contacted device: i) Zero-current measurements, have led to determine directly the evolution of the potential of the body (Figure 1), disclosing the conditions were the accumulation of positive charge rises the body potential up the point where the body-to-source junction is triggered. ii) Zero-potential measurements, draining the impact ionization hole current through the body-contact. This has allowed a precise reconsideration of the commonly accepted models to describe the phenomenon (Figure 2). From our study, an updated set of constants have been extracted for the calibration of the models [3]. The updated models (Selberherr and Crowell-Sze impact ionization [4]) have been validated comparing experimental data with commercial ATLAS-Silvaco simulations (Figure 3) for devices with different channels lengths and bias conditions. The outcome of this work provides further insight on the I.I. in thin and ultrathin SOI devices, developing a new protocol for its electrical characterization. The updated models will be essential for the proper description of the phenomenon in TCAD tools. [1] B. Vandana, International Journal of Modern Engineering Research, (IJMER), 2013. [2] S. Cristoloveanu, S. Li, Kluwer Academic Publishers, 1999. [3] S. Krishnan and J.G. Fossum, Solid-State Electronics, 39, 5, 1996. [4] Atlas users manual, Silvaco International 2010. Figure 1

Far-infrared radiation from n-InGaAs/GaAs quantum-well heterostructures in high lateral electric fields under injection conditions

The infrared radiation emitted by hot electrons in n-InGaAs/GaAs quantum-well heterostructures subjected to a lateral electric field is investigated under conditions of carrier injection from the current contacts. In structures with double tunneling-coupled wells one of which is δ-doped, a pronounced increase in the intensity of far-infrared radiation upon the onset of carrier injection is observed. At the same time, this effect is lacking in single-quantum-well structures with doped wells or barriers. The observed increase in the radiation intensity is associated with the direct intersubband transitions of electrons which contribute to emission upon the real-space transfer of charge carriers between wells. The intensity of these transitions increases due to compensation of the space charge existing between the wells by the injected holes.

Ambipolar Conduction Behavior on High Performance Schottky Barrier Source/Drain Gate-All-Around Si Nanowire Nonvolatile SONOS Memory

A Novel structure and high performance of the Schottky barrier source/drain gate-all-around (GAA) poly-Si nanowire (SiNW) nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory cell is reported with transistor characteristics, efficient programming/erasing, and reliability. The non-uniform thermal stress distribution on SiNW channel due to thermal insulation from the substrate by the buried oxide layer could affect carrier transport behavior. Under a high lateral electric field, the impact ionization is found since a large lateral field enhances carrier velocity. As gate voltage increases, the difference of the drain current between higher and room temperatures can be reduced because a high gate field lowers the Schottky barrier height of source/drain to ensure a strong hot-carriers generation. In particular, the ambipolar conduction of the Schottky barrier source/drain devices promotes the amount of hot-electron injecting programming by positive gate voltage, whereas the Schottky barrier enhances the generation of hot-holes at negative gate voltage to carry out erasure. The proposed Schottky barrier SONOS memory device provides low-voltage and high efficiency programming/erasing without apparent degradation of data retention and 10-K cycling endurance.

Lateral transport and far-infrared radiation of electrons in In x Ga1 − x As/GaAs heterostructures with the double tunnel-coupled quantum wells in a high electric field

It is shown that the far-infrared radiation of electrons in the selectively doped heterostructures with double tunnel-coupled quantum wells in high lateral electric fields strongly depends on the level of doping of the wells. At a high impurity concentration in a narrow well, higher than (1−2) × 1011 cm−2, the radiation is caused only by indirect intrasubband electron transitions. At a lower concentration, along with the indirect transitions, the direct intersubband transitions also contribute to the radiation. These transitions become possible in high electric fields due to the real-space electron transfer between the quantum wells.

Effect of a Channel Length and Drain Bias on the Threshold Voltage of Field Enhanced Solid Phase Crystallization Polycrystalline Thin Film Transistor on the Glass Substrate

AbstractWe have fabricated a new magnetic field enhanced solid phase crystallization (FESPC) polycrystalline silicon (poly-Si) thin film transistors (TFTs), which shows the excellent electrical characteristics and superior stability compared with hydrogenated amorphous silicon (a-Si:H) TFTs. The mobility (μ) and threshold voltage (VTH) of p-type TFTs of which the channel width and length are 5 μm and 7 μm, respectively are 31.98 cm2/Vs and -6.14 V, at VDS=-0.1 V. In the FESPC TFTs, the characteristics caused by grain boundary are remarkable due to large number of grain boundaries in the channel compared with poly-Si TFTs. The VTH of the TFT which have 5 μm channel length is smaller than that of 18 μm channel length by 1.36 V, which is considerably large value. It is due to the large number of grain boundaries in the channel and the high lateral electric field. The grain boundary potential barrier height is decreased, when the large lateral electric field is applied (which is called DIGBL effect). As a result of increased mobility, the drain current is increased, and VTH can be decreased. The activation energy (Ea) is strongly depended on the drain bias and the number of grain boundaries. is decreased, caused by the large drain bias and/or smaller number of grain boundaries. This decreased Ea can be reduced VTH due to increased the drain current. VTH of p-type poly-Si TFT employing FESPC on the glass substrate is affected by channel length and VDS due to energy barrier lowering effect at the grain boundary by increased lateral electrical field.

Analytical I-V relationship incorporating field-dependent mobility for a symmetrical DG MOSFET with an undoped body

A simple expression explicitly relating the surface potential to the surface electric field of a symmetrical double-gate (DG) MOS capacitor is proposed. The expression does not contain the floating-body potential as an implicit variable. It is used to derive, assuming the validity of the gradual-channel approximation, an analytical model expression for the current-voltage relationship of a DG MOS field-effect transistor. The effects of mobility degradation at high vertical electric field and velocity saturation at high lateral electric field are incorporated. The model expression is continuously valid from the subthreshold to the quasi-linear regimes of operation and up to a well-defined drain saturation voltage. Beyond this saturation voltage, the gradual-channel approximation breaks down within a region near the drain end of the channel. The electric-field distribution within this region is estimated by solving a two-dimensional Poisson's equation. Further implications of the model are derived by simplifying the expression in different regimes of operation using various approximations.

Monte Carlo simulation of hot electron transport in quantum well heterostructures under Γ–L intervalley transfer

Monte Carlo simulations of electron transport in AlxGa1−x As/GaAs/InyGa1−yAs double quantum well heterostructures in high lateral electric fields are carried out. It is shown that, under the conditions of intervalley Γ–L electron transfer, there exists a population inversion between the first and the second quantum-confinement subbands in the Γ valley. The population inversion appears in fields exceeding 4 and 5.5 kV cm−1 at 77 and 300 K, respectively. The gain in a superlattice composed of such quantum wells is estimated to be on the order of 100 cm−1 for radiation with a wavelength of 12.6 µm.

Population inversion between Γ subbands in quantum wells under the conditions of Γ-L intervalley transfer

Monte Carlo simulations of electron transport in AlxGa1−xAs/GaAs/InyGa1−yAs double-quantum-well heterostructures in high lateral electric fields are carried out. It is shown that, under the conditions of intervalley Γ-L electron transfer, there exists a population inversion between the first and the second quantum-confinement subbands in the Γ valley. The population inversion appears in the fields exceeding 4 and 5.5 kV/cm at 77 and 300 K, respectively. The gain in a superlattice composed of such quantum wells is estimated to be on the order of 100 cm−1 for radiation with a wavelength of 12.6 µm.

High hole mobilities in fully-strained Si/sub 1-x/Ge/sub x/ layers (0.3>x>0.4) and their significance for SiGe pMOSFET performance

Materials studies, hole transport measurements, and process and device simulations have been employed to determine the optimum epitaxial architecture of a fully-pseudomorphic Si/SiGe pMOSFET heterostructure that is intended for application in a near-standard CMOS process. Numerical simulations have shown that SiGe inter-diffusion severely limits the Ge content that can be achieved in a practical process flow. The SiGe hole wave-functions have been calculated and it is shown that hole confinement effects become very significant for SiGe layers less than 5 nm thick. Furthermore, estimates of the barrier penetration by the hole wave-function indicate that the beneficial effects of the buried-channel structure upon the hole mobility would be significantly reduced for Si cap thickness less than 2 nm. Buried-channel SiGe pMOSFETs are known to suffer from parallel conduction in the Si capping layer and calculations of the charge distribution indicate that high Ge contents (>30%) and thin Si cap thickness (<3 nm) are required in order to confine all of the inversion charge to the SiGe layer. The hole drift mobility has been measured at room temperature for fully-strained Si/sub 1-x/Ge/sub x/ layers with a range of alloy contents (0.3<x<0.4), and with hole densities between 3/spl times/10/sup 11/ cm/sup -2/ and 4/spl times/10/sup 12/ cm/sup -2/. The measured room temperature mobilities are consistently higher than the equivalent Si inversion layer mobilities and these results have been incorporated into two-dimensional (2-D) device simulations in order to understand their significance for SiGe pMOS device performance. It is found that improvements in current drive can be obtained, but only for the most aggressive vertical architectures. For Si cap thickness greater than 1.5 nm, parallel conduction in the cap layer counteracts much of the advantage of the high mobility channel and, even for thin Si caps, velocity saturation effects at high lateral electric fields significantly limit the current drive of a SiGe pMOSFET to values close to that of the conventional Si device. The diminished gate control, due to the inclusion of the cap layer, and the smaller SiGe bandgap also lead to a significant deterioration of the subthreshold characteristics.

Diagnostics of the hot-hole distribution function in quantum wells in a strong electric field

Modulation of the fundamental absorption edge by a high lateral electric field in a p-type In0.21Ga0.79As/GaAs heterostructure with quantum wells was studied at 4.2 K and electric fields as high as 1.9 kV/cm. The field-induced change in the symmetric part of the hole distribution function was measured.