High-k Spacer Research Articles

Exploration of symmetric high-k spacer (SHS) hybrid FinFET for high performance application

This paper evaluates the novelty aspects of symmetric high-k spacer (SHS) hybrid FinFET over conventional FinFET. The SHS hybrid FinFET combines three significant and advanced technologies i.e., 2-D ultra-thin-body (UTB), 3-D FinFET, and high-k spacer on a single silicon on insulator (SOI) platform to enhance the device performance. In these recent days, high-k dielectric spacer materials are widely explored because of their better electrostatic control and more immune towards short channel effects (SCEs) in nanoscale devices. For the first time, this paper introduces SHS hybrid FinFET and claims a useful improvement in device performances. Various parameters like subthreshold slope (SS), on–off ratio (Ion/Ioff), transconductance (gm), transconductance generation factor (TGF), gain (gm/gd), total gate capacitance (Cgg), and cut-off frequency (fT) are carefully observed with the variation of high-k spacer length (Lhk) ranging from 1 to 5 nm for the hybrid FinFET. From comprehensive 3-D device simulation, we have demonstrated that the proposed device is superior in suppressing SCEs with predicting higher drive current as compared to conventional FinFET.

Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability Analysis

High-k spacer materials have been extensively studied nowadays for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance. Interestingly, this paper demonstrates effective reduction in circuit delay with an optimum usage of high-k spacer material. An asymmetric dual-k spacer trigate (ADS-TG) FinFET architecture is employed for the purpose. From extensive 3-D simulations, it is demonstrated that ADS-TG device significantly improves the overall circuit delay and robustness performance while fully capturing the fringe capacitance effects. A FinFET inverter and a three-stage ring oscillator (RO3) are adopted to investigate the performances carefully. In comparison with the conventional device, the ADS-TG device speeds up the RO3 circuit by 22.6% and 32.4% using high-k spacer dielectrics HfO2 and TiO2, respectively. Contradictorily, a purely high-k FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the effects of supply voltage and underlap length on ADS-TG-based RO3 delay over the conventional ones are also dealt in. The ADS-TG device and static RAM based on this device prove to be more variation tolerant in comparison with the conventional configurations.

Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs

In this paper, we propose an optimized design for Si-nanowire FETs in terms of spacer dielectric constant (κsp), extension length (LEXT), nanowire diameter (Dnw), and operation voltage (VDD) for the sub-10 nm technology node. Using well-calibrated TCAD simulations and analytic RC models, we have quantitatively evaluated geometry-dependent parasitic series resistances (RSD) and capacitances (Cpara). Compared with low-κ spacers, high-κ spacers exhibit a higher on/off-current ratio with a lower RSD, but show severe degradation in their AC performance owing to a higher Cpara. Considering the trade-off between RSD and Cpara, optimal geometry-dependent κsp values at various supply voltages (VDD) are determined using gate delay (CV/I) and current-gain cutoff frequency (fT). We found that as LEXT and VDD decrease and Dnw increases, the optimal κsp value shifts from the high-κ to low-κ regime.

Suppression of subthreshold characteristics variation for junctionless multigate transistors using high-k spacers

In this work, the high-k spacer is proposed to suppress the subthreshold characteristics variation of junctionless multigate transistor (JMT) with non-ideal sidewall angle for the first time. It is demonstrated that the variation of subthreshold characteristics induced by the changing sidewall angle is efficiently suppressed by high-k spacers due to the enhanced corner effect through the fringe capacitance, and the electrostatic integrity of JMTs is also improved at sub-22 nm gate length. Two key parameters of high-k spacer, the thickness and length, have been optimized in terms of the suppression of subthreshold characteristics variation. Then their optimal values are proposed. The benefit of high-k spacer makes JMTs more scalable.

Investigation of Symmetric Dual-<inline-formula> <tex-math notation="TeX">\(k\) </tex-math></inline-formula> Spacer Trigate FinFETs From Delay Perspective

During recent years, high-k spacer materials have been extensively studied for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance that restricts researchers using these devices in high-performance circuits. For the first time, this paper demonstrates the usage of high-k spacer material with an optimized length for effective reduction of circuit delay and an improvement in robustness. An improvised symmetric dual-k spacer (SymD-k) underlap trigate FinFET architecture termed as SymD-k is employed for this purpose. From extensive 3-D simulations, this paper demonstrates that SymD-k device significantly improves overall circuit delay and robustness (noise-margins) with fully capturing the fringe capacitance effects. A CMOS inverter and a three-stage ring-oscillator (RO3) are adopted to carefully investigate the performances. In comparison with the conventional device, the SymD-k device speeds up the RO3 circuit by 27% and 33% using high-k spacer dielectric HfO 2 and TiO 2 , respectively. However, a purely high-k FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the effect of underlap length and supply voltage on SymD-k-based RO3 delay over the conventional ones are also dealt in.

Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k=7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (gm), the gain per unit current (gm/Ids), the intrinsic gain (gmRo), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, gm/Id and gm are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.

Analysis of Harmonic distortion in asymmetric underlap DG-MOSFET with high-k spacer

In analog and RF circuit applications Harmonic distortion (HD) is an important reliability issue that arises due to non-linear performance of devices. In this paper, the asymmetric underlap double gate MOSFET (AUDG-MOSFET) is analyzed for the HD with high-k spacers. In this analysis the devices are compared for their primary distortion components designated by the second order distortion (HD2), the third order distortion (HD3) and the total harmonic distortion (THD). The distortion characteristics of the device are studied as a function of the gate voltage (Vgs) and the transconductance generation factor (gm/Id) considering the influence of drain current (Id) and the transconductance (gm). A significant improvement on the HD of the device by using high-k spacers is inferred, thereby ascertaining better reliability for RF applications. In addition to this, the distortion in the output characteristics of Cascode and differential amplifier circuits designed with AUDG-MOSFET device is also analyzed in detail.

Design and Analysis of Analog Performance of Dual-k Spacer Underlap N/P-FinFET at 12 nm Gate Length

Among the multigate structures, FinFET is emerging as a promising candidate due to its better gate electrostatic control and ease of manufacturability. However, loss of gate electrostatic integrity (EI) is still observed in FinFET while it is scaled down to nano-scale regime, resulting in deterioration of analog performance. Most importantly, precise dimensional requirements and process challenges are major hurdles at nano-scale regime resulting in device-to-device variability. Nevertheless, efficient use of gate sidewall fringing fields, by use of an inner high-k spacer, can restore the loss of gate control. In this paper, we observe that, due to excellent gate EI, the analog performance of dual-k spacer-based underlap N/P-FinFET is better than the conventional low-k N/P-FinFET. Simulation results at 12 nm gate length reveal that dual-k N/P-FinFETs are capable of targeting high-gain, low-power, and moderate frequency of operation even with lower aspect ratio (fin height/fin width) and higher fin width, oxide thickness, and lateral straggle. In addition, the figures of merit of dual-k N/P-FinFETs are less variable to major parametric variations such as fin width and oxide thickness. These attractive features prove to be handy in designing circuitry for low-power battery-operated portable gadgets.

Dual-dielectric-constant spacer hetero-gate-dielectric tunneling field-effect transistors

Hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) with dual-dielectric-constant (k) spacers have been fabricated and characterized. They have a heterogeneous gate dielectric layer which consists of high-k material (HfO2) and SiO2 at the source and drain side, respectively. The dual-k spacer has an inner high-k and outer SiO2 spacer. The fabricated dual-k-spacer HG TFETs show higher on/off current ratio, on-current and better subthreshold slope than control TFETs which use only SiO2 for a gate dielectric layer and spacer. Moreover, the impact of the length of high-k material inserted under the gate (Lhigh-k) has been investigated. It turns out that the optimization of Lhigh-k can significantly improve performance and power efficiency.

Impact of high-k spacer on device performance of a junctionless transistor

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I D ), ON-state to OFF-state current ratio (I ON /I OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G m R O ), output conductance (G D ), transconductance/drain current ratio (G m /I D ) and unity gain cut-off frequency (f T ). The effects of varying the spacer dielectric constant (k sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.

Impact of dual-k spacer on analog performance of underlap FinFET

Multigate structures have better short channel control than conventional bulk devices due to increased gate electrostatic control. FinFET is a promising candidate among multigate structures due to its ease of manufacturability. The RF performance of FinFET is affected by gate controlled parameters such as transconductance, output conductance and total gate capacitance. In this paper we have used dual-k spacers in underlap FinFETs to improve the gate electrostatic integrity. The inner high-k spacer helps in better screening out the gate sidewall fringing fields, thereby, increasing transconductance and reducing output conductance with increase in total gate capacitance. At 16nm gate lengths, we have observed that, the intrinsic gain of dual-k spacer based FinFET can be increased by more than 100% (>6dB) without affecting cutoff frequency and maximum oscillation frequency, as compared to conventional single spacer based FinFET. Improvement in cutoff frequency by 11% and maximum oscillation frequency by 5% can be achieved, when the gate lengths are scaled down to 12nm, in addition to 2.75 times (8.8dB) increase in intrinsic gain.

Engineering spacers in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS logic circuits

In this paper, it has been shown that employing an underlap channel created by using the dual spacers in dopant-segregated Schottky barrier (DSSB) SOI MOSFET not only reduces the off-state leakage, short-channel effects and the parasitic overlap capacitances but also suppresses the variability induced by process fluctuations in the Schottky barrier height, dopant-segregation length and SOI film thickness of the device. However, the reduced effective gate voltage due to voltage drop across the underlap lengths also reduces the on-state drive current of the device. To alleviate this trade-off, a novel dual-k spacer underlap channel DSSB SOI structure has also been proposed in which the increased fringing electric field effect due to high-k inner spacer layer not only improves the on-state drive current but also reduces the off-state leakage current in both n-channel and p-channel devices. Despite the presence of high-k inner spacer layer increasing the fringing gate capacitance, the scalability in an optimized dual-k spacer underlap structure has improved by ∼60% and ∼35%, respectively over the conventional spacer overlap and underlap channel structures. In addition, the variability in an optimized dual-k spacer underlap structure has also been reduced by ∼50% and ∼30% respectively over the conventional spacer overlap and underlap channel structures. This clearly indicates that the proposed dual-k spacer underlap structure is a better choice for low-variability nanoscale CMOS logic circuits. The detailed fabrication flow of this novel device has also been proposed which demonstrates the use of conventional CMOS processes.

Modeling the impact of junction angles in tunnel field-effect transistors

We develop an analytical model for a tunnel field-effect transistor (TFET) with a tilted source junction angle. The tunnel current is derived by using circular tunnel paths along the electric field. The analytical model predicts that a smaller junction angle improves the TFET performance, which is supported by device simulations. An analysis is also made based on straight tunnel paths and tunnel paths corresponding to the trajectory of a classical particle. In all the aforementioned cases, the same conclusions are obtained. A TFET configuration with an encroaching polygon source junction is studied to analyze the junction angle dependence at the smallest junction angles. The improvement of the subthreshold swing (SS) with decreasing junction angle can be achieved by using thinner effective oxide thickness, smaller band gap material and longer encroaching length of the encroaching junction. A TFET with a smaller junction angle on the source side also has an innate immunity against the degradation of the fringing field from the gate electrode via a high-k spacer. A large junction angle on the drain side can suppress the unwanted ambipolar current of TFETs.

MODELING GATE CURRENT FOR NANO SCALE MOSFET WITH DIFFERENT GATE SPACER

Dimensions of metal–oxide–semiconductor field effect transistor (MOSFET) have been scaled down for decades to maintain the performance. So, as a result of aggressive scaling, gate oxide thickness approaches its manufacturing and physically limiting value of less than 2 nm in nano regime. Under such circumstances, gate leakage (tunneling) current has become a critical problem in nano domain as compared to subthreshold leakage current. Consequently, accurate quantitative understanding of gate tunneling leakage current is very important especially in context of low power VLSI application. In this work, gate tunneling currents have been modeled including the inevitable nano scale effects for a MOSFET having different high-k dielectric spacer such as SiO2 , Si3N4 , Al2O3 , HfO2 . The gate current model is compared and contrasted with santaurus simulation results and reported experimental result to verify the accuracy of the model. The agreement found was good, thus validating the developed analytical model. It is observed that neglecting nano scale effects may lead to large error in the calculated gate current. It is found in the results that gate leakage current decreases with the increase of dielectric constant of the gate spacer. Further, it is also reported that the spacer materials impact the threshold voltage, on current, off current, drain induced barrier lowering, and subthreshold slope of the device.

Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor With High- $\kappa$ Spacers

We propose the use of a high-κ spacer to improve the electrostatic integrity and, thereby, the scalability of silicon junctionless transistors (JLTs) for the first time. Using extensive simulations of n-channel JLTs, we demonstrate that the high-κ spacers improve the electrostatic integrity of JLTs at sub-22-nm gate lengths. Electric field that fringes through the high-κ spacer to the device layer on either sides of the gate results in an effective increase in electrical gate length in the off-state. However, the effective gate length is unaffected in the on-state. Hence, the off-state leakage current is reduced by several orders of magnitude with the use of a high-κ spacer with concomitent improvements in the subthreshold swing and drain-induced barrier lowering. A marginal improvement in the on-state current is observed with the use of the high-κ spacer, and this is related to the reduction in parasitic resistance in the silicon under the spacer due to fringe fields.

Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D (source/drain) region. It is found that an optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and drain induced barrier lowering (DIBL) characteristics. It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.

Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behavior of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended source/drain region. It is found that optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and drain induced barrier lowering characteristic with a slight degradation in source/drain series resistance and effective gate capacitance.

Use of DBARCs Beyond Implant

Almost a decade ago, the integrated circuit (IC) industry realized that traditional implant layers required new technology to achieve the specifications of the shrinking design rules and increased topography effects. In response, developer-soluble bottom anti-reflective coatings (DBARCs) were introduced as a solution. DBARCs offered the resolution and critical dimension (CD) control needed for the increasingly critical implant layers. In this paper the benefits DBARCs can bring to other lithographic processes are reviewed. Back-end-of-line (BEOL) dual damascene processes are surveyed. Front-end-of-line (FEOL) processes are examined, including high-k metal gate (HKMG), double patterning, and spacer. All processes are defined, and the value that a DBARC brings to each process is examined, along with potential challenges.

Impact of Gate Engineering on Gate Leakage Behavior of Nano Scale MOSFETs with High-k Dielectrics

This paper discusses the gate leakage current characteristics based on gate tunnel model for different device structure having high-k dielectric as a gate dielectric and/or a spacer. In this study, a device structures are characterized to reduce the gate leakage current based on gate dielectric and the spacer structures. Several structures were also studied for other electrical performance parameters like on current, off current, drain induced barrier lowering (DIBL), subthreshhold slope(SS). The device structure in which the high-k dielectric extends to the bottom of the oxide spacers showed the smallest gate leakage current while the device structure in which gate dielectric is of high-k material and spacer is of silicon dioxide showed the best DIBL, SS, on current and off current characteristics.

Dopant-Segregated Schottky Source/Drain Double-Gate MOSFET Design in the Direct Source-to-Drain Tunneling Regime

The effect of direct source-to-drain tunneling (DSDT) on dopant-segregated Schottky (DSS) source/drain double-gate MOSFET design is investigated. In the DSDT regime, graded source/drain doping profiles offer improved device performance due to increased DSDT barrier width. Non-zero Schottky barrier heights also offer some performance improvement for the same reason, but high-k gate-sidewall spacers are a much better alternative. Ultimately, DSDT and short channel effects will limit the scaling of the (off -state) electrical channel length, which is determined by the source-to-drain contact spacing and fringing field effects such as gate sidewall coupling and silicide gating. Although the physical gate length can be scaled below 3 nm with little DSDT-induced performance degradation, the lower limit for source-to-drain contact spacing is projected to be ~ 11 nm.