Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability Analysis

Abstract

High-k spacer materials have been extensively studied nowadays for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance. Interestingly, this paper demonstrates effective reduction in circuit delay with an optimum usage of high-k spacer material. An asymmetric dual-k spacer trigate (ADS-TG) FinFET architecture is employed for the purpose. From extensive 3-D simulations, it is demonstrated that ADS-TG device significantly improves the overall circuit delay and robustness performance while fully capturing the fringe capacitance effects. A FinFET inverter and a three-stage ring oscillator (RO3) are adopted to investigate the performances carefully. In comparison with the conventional device, the ADS-TG device speeds up the RO3 circuit by 22.6% and 32.4% using high-k spacer dielectrics HfO2 and TiO2, respectively. Contradictorily, a purely high-k FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the effects of supply voltage and underlap length on ADS-TG-based RO3 delay over the conventional ones are also dealt in. The ADS-TG device and static RAM based on this device prove to be more variation tolerant in comparison with the conventional configurations.