High-k Spacer Research Articles

Improvement of digital, analog/RF and linearity performances of charge plasma based junctionless FinFET through spacer layer engineering

We investigate the digital, analog/RF, and linearity performance of four CP FinFETs distinguished by spacer layers: (i) single low-k spacer on both sides of the gate (D1), (ii) single high-k spacer on both sides of the gate (D2), (iii) a combination of high-k spacer and air on the source side and high-k spacer on the drain side (D3), and (iv) a combination of high-k spacer and air symmetrically placed on both sides of the gate (D4) at 10 nm technology node. Our results highlight the superior digital performance of the D4 device, demonstrating significant enhancements in various analog/RF figures of merit (FOMs) including transconductance, transconductance efficiency, unity gain cut-off frequency (FT), and gain bandwidth product (GBP). Notably, the D4 device exhibits a remarkable 256 % improvement in FT and a substantial 456.13 % enhancement in GBP compared to D1. Additionally, we analyze linearity and intermodulation distortion performance, suggesting the D4 device as the optimal architecture for high-performance digital and analog/RF applications.

Self-Consistent LCAO Based DFT Analysis of High-k Spacers and its Assessment on Gate-Stacked NCFET for Improved Device-Circuit Performance

Self-Consistent LCAO Based DFT Analysis of High-k Spacers and its Assessment on Gate-Stacked NCFET for Improved Device-Circuit Performance

Design of high-K dielectric HSS-DMG Junctionless FinFET using hetero GOS for nanoscale application

This article presents a detailed investigation of the High-K dielectric horizontal stack spacer (HSS) dual material gate junction-less FinFET device for analog and RF application using the gate oxide stack (GOS) approach. At first, the impact of the horizontal stack spacer (HSS) with different high-K spacer materials are investigated by placing different dielectric material like HfO2, SiO2, Si3N4, and TiO2 on the horizontal spacer. The simulation results of the device indicate that the High-K dielectric HSS makes the device high stability toward the leakage current and static power dissipation at the sub-nano scale regime. The DC characteristics of the device are also investigated alongside the AC/RF characteristics. The proposed device predominantly improves performance in terms of parameters like subthreshold swing, Ion/Ioff, and DIBL. The proposed device shows a high ON current of 8.56 × 10−5 A μm−1, which is about 15% higher than the existing literature, and the device also makes a notable impact on the leakage current by restricting it to 9.635 × 10−12 A/μm. The simulation of the device is carried out with optimization of the doping to investigate and improve the device’s performance. The device shows an excellent improvement in performance which is highly suitable for future-ready device applications.

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.

Investigation of spacer-engineered stacked nanosheet tunnel FET with varying design attributes

The stacked nanosheet field-effect transistors (SNS-FETs) are potential contenders for sub-7 nm technology. Device miniaturization leads to a larger off-state current and a higher subthreshold slope in SNS-FETs. Unlike SNS-FETs, the stacked nanosheet tunnelling field effect transistors (SNS-TFETs) function as switches in integrated circuits, featuring high performance and low power consumption. The endeavour aims to investigate how each design parameter optimises the switching characteristics of the SNS-TFET device. This paper examines various design attributes, such as different dielectric spacer materials, nanosheet width (NW), nanosheet thickness (NT), source doping, drain doping, etc. The Cogenda Visual TCAD serves as a tool for conducting device simulations. According to the simulation study, the use of a high-k hafnium dioxide (HfO2) spacer produces a higher switching ratio ( 7.28×1011 ) and a lower subthreshold swing (20.303 mV/decade). Using either low-k or no spacers reduces the overall gate capacitance and unit frequency gain compared to high-k spacers. Upscaling the nanosheet width (10 to 50 nm) enhances the switching ratio by 1.11×101 and transconductance by 61.92%. Downscaling the nanosheet thickness (6 to 4 nm) at the optimized nanosheet width (50 nm) improves the switching ratio by 1.88. Increasing the gate length from 8 to 16 nm reduces the leakage current by 2.34×10−2 A and improves the switching ratio by 2.90×101. An increase in the source doping level from 1×1020 to 5×1020 cm−3 results in a 1.07×102 decrease in the switching ratio and a 2.48-fold increase in the subthreshold swing. Furthermore, the findings indicate that drain doping is crucial in determining ambipolar current. In SNS-TFET, ambipolar current reduces significantly when drain doping is 1×1017 cm−3. Thus, the proposed work addresses the limitations of scaling and optimised design parameter characteristics for low-power nanoscale circuits.

Exploration of underlap induced high-k spacer with gate stack on strain channel cylindrical nanowire FET for enriched performance

This research explores a comprehensive examination of gate underlap incorporated strained channel Cylindrical Gate All Around Nanowire FET having enriched performances above the requirement of the 2 nm technology node of IRDS 2025. The device installs a combination of strain engineering based quantum well barrier system in the channel region with high-k spacers sandwiching the device underlaps and stack high-k gate-oxide. The underlaps are prone to parasitic resistance and various short channel effects (SCEs) hence, are sandwiched by HfO2 based high-k. This SCE degradations and a strong electric field in the drain-channel region is rendered controlling the leakages. The strain based Nanosystem engineering is incorporated with Type-II heterostructure band alignment inducing quantum well barrier mechanism in the ultra-thin cylindrical channel region creating an electrostatic charge centroid leading to energy band bending and splitting among the two-fold and four-fold valleys of the strained Silicon layer. This provides stupendous electron mobility instigating high current density and electron velocity in the channel. Thereby, the device is susceptible to on-current enhancement via ballistic transport of carriers and carrier confinement via succumbing of quantum charge carriers. The device transconductance, Ion, Ioff, Ion/Ioff ratio are measured and the output performance (ID-VDS) characteristics is determined providing emphatic enrichments in contrast to the existing gate all-around FETs as well as the 2 nm technology node data of IRDS 2025. Hence, the strained channel Nanowire FET device developed here is presented here as the device of the future for various digital applications, RF applications and faster switching speed.

Oppositely-Doped Core-Shell Junctionless Nanowire FET: Design and Investigation

Junctionless Nanowire Field Effect Transistor (JL-NWFET) has garnered significant attention in recent years owing to its simplified fabrication process, achieved through uniform doping across the device. However, JL-NWFET suffers from certain drawbacks, including low drive current, insufficient volume depletion, and lateral band-to-band tunneling. To address these issues, this paper proposes Improved JL-NWFET with an oppositely doped core–shell structure along with a Dual Material gate (DMG) and high-k spacer. Furthermore, Improved JL-NWFET is optimized for parameters such as core thickness, gate oxide material, spacer material, and spacer length. The performance of Improved JL-NWFET is also evaluated in comparison with other structural variants of JL-NWFET. Notably, Improved JL-NWFET showcases an enhancement of 23.1% and 20% in ON-state current (I ON ) and transconductance (g m ), respectively when compared to the conventional JL-NWFET. Furthermore, the Subthreshold Slope (SS) experiences an 88% improvement in the Improved JL-NWFET as opposed to the JL-NWFET. Additionally, the OFF-state leakage current (I OFF ) undergoes a fivefold reduction, leading to a sixfold increase in the I ON /I OFF ratio compared to the JL-NWFET. Among all the variants of JL-NWFET devices analyzed in this paper, Improved JL-NWFET stands out with its exceptional performance characteristics.

Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective

This manuscript presents a performance analysis of 3-stack JL-NWFETs with different spacer materials and spacer lengths. The DC and analog/RF performance is analysed at the device level, and circuit level. In single-k spacer analysis, TiO2 exhibits lowest IOFF of ∼89.28%, and largest ION/IOFF ratio with better subthreshold performance of ∼42.51% as compared to Air spacer at Lext = 7 nm. In addition, TiO2 spacer is suitable for analog applications while Air spacer for RF applications. The dual-k spacer analysis is also performed and the TiO2+Air spacer showed prodigious DC/Analog/RF performances dominating all other combinations. Further investigations into inner high-k spacer analysis (Lsp,hk) revealed that higher Lsp,hk is suitable for DC and Analog applications whereas lower Lsp,hk for RF applications. The CS amplifier designed for configurations of Lsp,hk showed better gain for higher Lsp,hk with the amplification gain of ∼4.8 V/V. Overall, this analysis serves as a beacon, guiding the future of JL-NWFET design for spellbinding nano-electronic devices at sub-5nm technology node.

Engineering negative differential resistance in negative capacitance Quad-FinFET

In this work, a systematically analysis of the Negative Capacitance (NC) Quad-FinFET structure is carried out where we determine the optimal FE layer thickness that enables hysteresis-free transfer characteristics. However, negative differential resistance (NDR) is introduced along with the increased FE-layer thickness, which is not desirable for application in analogcircuits. Through the implementation of an asymmetric drain length extension and a high-k Si3N4 spacer, negative differential resistance (NDR) can be mitigated. In addition, the relatively poor analog performance generally seen in conventional FinFET structures are overcome in the drain engineered NC Quad-FinFET structure with gate spacer resulting in significant improvement in performance parameters such as transconductance, output conductance and intrinsic gain. The integration of NC Quad-FinFET as a digital inverter is carried out where the circuit propagation delay is decreased by 27.65% with drain length extension and inclusion of Si3N4 spacer. Thus, through these device optimization techniques, the NC Quad-FinFET structure shows significant improvement in both analog and digital device performance parameters.

Performance analysis of nanosheet transistor with drain/source extension and high-k spacer optimizations for analog applications

Performance analysis of nanosheet transistor with drain/source extension and high-k spacer optimizations for analog applications

Design and analysis of asymmetrical low-k source side spacer halo doped nanowire metal oxide semiconductor field effect transistor

In this paper, we propose a low-k source side asymmetrical spacer halo-doped nanowire metal oxide semiconductor field effect transistor (MOSFET) design and analysis. High-k spacer materials are now being researched extensively for improving electrostatic control and suppressing short-channel effects in nanoscaled electronics. However, the high-k spacers' excessive increase in fringe capacitance degrades the dynamic circuit performance. Surprisingly, this approach achieves a significant reduction in gate capacitance by maximizing the use of high-k spacer material. Three different structures, symmetrical dual-k spacer, low-k drain side asymmetrical spacer, low-k source side asymmetrical spacer halo doped nanowire MOSFET architectures are simulated and among them low-k source side asymmetrical spacer halo doped nanowire MOSFET architecture giving lower gate capacitance. After doing 3D simulations in Silvaco technology computer-aided design (TCAD) we observed that the gate capacitance and intrinsic delay are 1.23x10<sup>-17</sup> farads and 1.11x10<sup>-12</sup> seconds respectively for low-k source side asymmetrical spacer architecture and these are less as compared to high-k spacer architecture. So, the proposed structure is highly recommended for digital applications.

Performance Analysis of Gate Engineered High-K Gate Oxide Stack SOI Fin-FET for 5 nm Technology

Abstract: This paper analyses the performance of 5 nm gate length gate engineered oxide stack silicon on insulator (SOI) fin field-effect transistor (OS-Fin-FET) for the first time. The high dielectric (High-K) value of the material-based gate oxide stack structure increases both the analog and the radio frequency (RF) performance of the Fin-FET device when compared to standard single gate oxide material structures. The work function of the engineered gate structure further helps in advancing the performance of the device in terms of on current (Ion), off current (Ioff) and the ratio of Ion/Ioff. The proposed OS-FinFET device improves on current (Ion) of the device by 12% in comparison to the high-K dielectric gate oxidebased FinFET device. Simulation of the device is further extended to study different electrical characteristics of the proposed device under other biasing conditions, to estimate enhanced analog and RF performance where the device is highly suitable for low power and high-speed applications. Overall, the proposed device shows improvement in existing architectures of the devices. Technology computer-aided design (TCAD) tool is used to perform entire simulations of the proposed device with 5 nm gate length. Aim: To enhance analog and RF performance of the Fin-FET device at 5 nm gate length. Background: Design of the sub-10 nm Fin-FET device undergoes charge shearing phenomena because of the minimum distance between source and drain. This problem is addressed by using High-K spacer over substrate but it leads to increase in the channel resistance and adverse short channel effects. A combination of different high-K dielectric materials can eliminate this performance. Hence most of the studies concentrated on spacer region and failed to consider channel region. This study tries to improve analog performance of the device using the approach of gate engineering with gate stack approach. Objective: The main objective of this study is to increase on current (Ion) of the device by implementing gate engineering approach, by choosing dual work function-based gate with oxide stack approach. The High-K dielectric material-based gate oxide reduces leakage current, decreases off current which will increase the ratio of Ion/Ioff. Methods: The dual work function gate material is taken with gate oxide stack approach by considering different High-K dielectric materials like HfO2, TiO2 with thin SiO2 layer as the interactive layer. Simulation of the device is carried out using TCAD Tool and results are compared with existing literature, to validate the results. Results: The proposed architecture of the Fin-FET device delivers excellent results in terms of on current and subthreshold characteristics compared to existing literature. The proposed device gives high on current of 0.027 A and current ratio of 1.08X104. Conclusion: A complete comparative analysis is carried out with existing literature on the proposed device, where the proposed device resulted in high performance. The proposed device improves 12% compared to existing literature, which is highly suitable for low power applications.

Analog Performance Analysis of High-K Spacer Dual Material Gate Graded Channel Nanotube

Analog Performance Analysis of High-K Spacer Dual Material Gate Graded Channel Nanotube

Performance Evaluation of Spacer Dielectric Engineered Vertically Stacked Junctionless Nanosheet FET for Sub-5 nm Technology Node

This manuscript for the first time provides insights on the impact of different spacer materials for the vertically stacked Junctionless Nanosheet Field Effect Transistor (JL-NSFET). The analog/RF performances of several single-k and dual-k spacers in two approaches namely (1) inner high-k + outer low-k and (2) inner low-k + outer high-k are explored at 3 nm gate length. It is noticed that the use of TiO2 spacer improves analog performance of the JL-NSFET whereas the usage of SiO2 improves the RF performance of the device when single-k spacer has been used. The intrinsic gain (Av) of the JL-NSFET is improved by ∼1.74× with TiO2 as compared to SiO2 spacer. Moreover, it is observed that the dual-k approach with inner high-k + outer low-k combination gives better analog/RF performances compared to inner low-k + outer high-k and single-k spacer combinations. Furthermore, the increase in length (Lsp,hk) of inner high-k spacer length provides improved analog characteristics at the marginal cost of RF performance.

Effects of Symmetric and Asymmetric Double-Layer Spacers on a Negative-Capacitance Nanosheet Field-Effect Transistor

The effect of three double-layer spacers (corner/selective/dual) on the performance of a negative-capacitance nanosheet field-effect transistor (NC-NSFET) was investigated for the first time. Sentaurus technology computer-aided design simulations revealed that the NC-NSFET with corner spacer will be significantly improved in transfer and high frequency characteristics due to the increase of ferroelectric layer thickness, and the NC-NSFET with a selective spacer structure exhibits better gate controllability. Compared with the ordinary dual-k spacer structure, the switching current ratio is doubled, and its subthreshold swing and drain-induced barrier lowering are reduced by 3.0% and 48%, respectively. In addition, by introducing a selective spacer at the source side and a corner spacer at the drain side, the NC-NSFET has a smaller intrinsic delay and exhibits better capacitance matching and stronger gate controllability than that with a symmetric spacer. For the double-layer spacer, the extension of the high-k spacer in the horizontal direction is more beneficial to the improvement of the device performance than that in the vertical direction, which provides a more comprehensive reference for the spacer application in NC-NSFET.

Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15 nm Gate Length

In this proposed work, performance of junctionless transistor with the use of spacers has been evaluated at 15 nm gate length in Cogenda TCAD tool. This work is implemented as variation in four parts: changing the spacer extension length, placement of spacers having dual-κ, proportion of low and high-κ spacers, and value of high-κ dielectric constant. Impact of all these parameters is considered on the output of proposed device in terms of various output parameters like on-current (ION), off-current (IOFF), subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (gm), transconductance generation factor (TGF), output conductance (gd), early voltage (Vea) and intrinsic gain (Av). From the simulations, it has been observed that placing spacers of dual-κ along the left and right sides of gate region has improved device performance in terms of output parameters. Due to increased gate capacitances, the increase in dielectric constant value has degraded the device performance for longer spacer extension length. However, for shorter spacer extension length, the device characteristics are improved as the value of dielectric constant is increased. Therefore a trade-off is required to get the optimum results of the device.

On the performance of hafnium-oxide-based negative capacitance FinFETs, with and without a spacer

This paper reports a thorough investigation of the impacts of a spacer dielectric on the performance of HfO2-ferroelectric-based negative capacitance (NC)-FinFETs for 10 nm technology (gate length 22 nm) as per International Roadmap for Devices and Systems with in comparison with similarly-sized conventional FinFETs by means of an industry standard technology computer aided design tool. It is found that, although a high-k spacer results in improved subthreshold swing (SS) and I ON, it increases delay due to enhanced gate capacitance for both types of devices. In spite of having higher gate capacitance for a given spacer, the delay is lower for the NC devices than the conventional devices with identical I OFF, which is due to higher I ON in such devices. Comparing with the baseline FinFET; I ON, SS, threshold voltage, delay and power dissipation of NC-FinFET have been found to improve by 69%, 7%, 5%, 14% and 9% respectively, when Si3N4 spacer is used. Implications of spacer on V DD scalability, delay and power dissipation of NC-FinFETs have also been investigated in one-to-one comparison with similarly-sized conventional FinFETs. If identical delay is considered in both the devices, higher active power dissipation due to enhanced gate capacitance is a concern for HfO2-ferroelectric-based NC-FinFETs.

Improving the Scalability of Ferroelectric FET Nonvolatile Memories With High-k Spacers

This paper investigates scaled ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) with high-k spacer device design considering ferroelectric-dielectric random phase variations with TCAD atomistic simulations. Our study indicates that, in addition to raising the orthorhombic phase and reducing the grain size of the ferroelectric, using high-k spacers can serve as another way to enhance the scalability of FeFETs because it improves both the mean memory window (MW) and the worst-case MW. More importantly, these improvements increase with the down-scaling of gate length. In addition, we have investigated the impact of high-k spacers on the critical electric field across interfacial layer (EIL) for the reliability of FeFET NVMs. Our study suggests that, for scaled FeFETs with high-k spacers, the highest EIL during write operation is no longer located near the S/D edge but at the mid channel. Using high-k spacers can reduce the mid-channel EIL, and the reduction increases with decreasing gate length due to the increasing impact of high-k spacers. Our study may provide insights for future high-density FeFET design.

P-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

Silicon (Si) nanosheet (NS) metal-oxide semiconductor field effect transistors (MOSFETs) are realized as an outstanding structure to obtain better area scaling and power performance compared to FinFETs. The Si NS MOSFETs provide high current drivability due to wider effective channel (W eff) and maintain better short channel performance. Here, the performance of junctionless (JL) SOI NS p-MOSFET is evaluated by invoking HfxTi1−xO2 gate stack to overcome adverse short channel effects (SCEs). The device performance is enhanced using various spacer dielectrics and the electrical characteristics are presented. Moreover, the effect of NS width variation on I ON/I OFF, SS, V th is presented and the analog/RF metrics of the device are evaluated. The power consumption, dynamic power, and static power analyses of NS MOSFET is presented with respect to the ITRS road map. Our investigation reveals that the device exhibits an I ON/I OFF ratio of more than ∼106 with NS widths of 10 to 30 nm, respectively. The device exhibits better performance (I ON) with higher NS widths and ensures potential towards high-performance applications. However, with an increase in NS widths the threshold voltage (V th) tends to downfall and leads to deterioration in subthreshold performance . With high-k spacer dielectric the device exhibits better static power consumption for the CMOS inverter. By careful control of NS width and effective usage of spacer dielectric ensures better p-MOSFET design for future technology nodes.

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Multi-fin devices are the most reliable option for terahertz (THz) frequency applications at nano-regime. In this work impact of spacer engineering on multi-fin SOI FET performance is evaluated by invoking single low-k (Air), high-k (Si3N4, HfO2), and hybrid dual-k (Air + Si3N4) spacer in the underlap section at nano-regime. The simulation study reveals that the high-k (HfO2) spacer gives a higher switching ratio (ION/IOFF) in the order of ~107, subthreshold swing (SS) = 72 mV/dec, drain induced barrier lowering (DIBL) = 22.14 mV/V and quality factor (Q) = g m /SS = 0.16 μS-dec/mV. Furthermore, to measure the suitability of the device for high frequency applications various analog/RF parameters are studied. The high-k (HfO2) spacer dominates DC and analog performance, whereas the low-k (Air) spacer dominates the RF domain with f T = 1.26 THz, GBW = 0.251 THz, TFP = 29 THz range, and with smaller intrinsic delays. Hybrid dual-k spacer (Air + Si3N4) outperforms in terms of gain (AV) and output resistance ( R o ). The Air spacer exhibits lower dynamic power of 2.09 aJ/μm and power consumption of 1.04 aJ/μm. The linearity metrics for multi-fin SOI FET parameters like g m 2 , g m 3 , HD1, HD2, THD, and VIP2 are also studied. The Air spacer followed by hybrid spacer outperforms in linearity, and harmonic distortion components and ensures its potential for RF applications at nano-regime.