Performance Evaluation of Spacer Dielectric Engineered Vertically Stacked Junctionless Nanosheet FET for Sub-5 nm Technology Node

Abstract

This manuscript for the first time provides insights on the impact of different spacer materials for the vertically stacked Junctionless Nanosheet Field Effect Transistor (JL-NSFET). The analog/RF performances of several single-k and dual-k spacers in two approaches namely (1) inner high-k + outer low-k and (2) inner low-k + outer high-k are explored at 3 nm gate length. It is noticed that the use of TiO2 spacer improves analog performance of the JL-NSFET whereas the usage of SiO2 improves the RF performance of the device when single-k spacer has been used. The intrinsic gain (Av) of the JL-NSFET is improved by ∼1.74× with TiO2 as compared to SiO2 spacer. Moreover, it is observed that the dual-k approach with inner high-k + outer low-k combination gives better analog/RF performances compared to inner low-k + outer high-k and single-k spacer combinations. Furthermore, the increase in length (Lsp,hk) of inner high-k spacer length provides improved analog characteristics at the marginal cost of RF performance.