High-k Gate Research Articles

Comprehensive analysis of determining factors of the effective work function of TiAlC/TiN metal gates for advanced gate-all-around CMOS integration

Abstract We have examined the determining factor of the effective work function (EWF) for an n-channel MOSFET (n-type EWF) in TiAlC/TiN metal gates on high-k gate dielectrics (HK). From electrical and physical evaluations of the bottom TiN between HK and TiAlC (BTM-TiN), the obtained results suggest that the dominant factor for the n-type EWF of TiAlC/TiN metal gates is not the fixed charge in the gate dielectric but the vacuum work function of BTM-TiN. It was found that TiN with low oxygen content has a vacuum work function of 3.8 eV, suitable for an n-channel MOSFET although TiN has been believed to be suitable for a p-channel MOSFET. We also found that its vacuum work function increases with increasing oxygen content. Based on these results, we proposed an oxygen scavenging from BTM-TiN(O) by Al in TiAlC as a novel mechanism for the n-type EWF for TiAlC/TiN metal gates.

High-performance van der Waals stacked transistors based on ultrathin GaPS4 dielectrics.

Exploring high-κ gate dielectrics is crucial for the achievement of high-performance field-effect transistors (FETs). Here, we report the synthesis of a few-layer wide bandgap semiconductor gallium thiophosphate (GaPS4), which can be easily mechanically exfoliated from a bulk material. The few-layered GaPS4 flakes exhibit a relative dielectric constant of approximately 5.3. Two-dimensional (2D) van der Waals heterostructure FETs utilizing atomically smooth GaPS4 flakes as the top-gate dielectric layer and MoS2 as the channel material were fabricated, showing a high on-off ratio exceeding 107 with a subthreshold swing as low as 80 mV per decade. Our findings indicate that few-layer GaPS4 is a high-performance dielectric candidate for two-dimensional transistors, which enrich the high-κ 2D community and pave the way for fabricating modern electronic devices.

High performance AlGaN/GaN MISHEMTs using N2O treated TiO2 as the gate dielectric

Abstract In this work, TiO2 thin films deposited by the atomic layer deposition (ALD) method were treated with a special N2O plasma surface treatment and used as the gate dielectric for AlGaN/GaN metal insulator semiconductor high electron mobility transistors (MISHEMTs). The N2O plasma surface treatment effectively reduces defects in the oxide during low-temperature ALD growth. In addition, it allows oxygen atoms to diffuse into the device cap layer to increase the barrier height and thus reduce the gate leakage current. These TiO2 films exhibit a dielectric constant of 54.8 and a two-terminal current of 1.96 × 10−10 A mm−1 in 2 μm distance. When applied as the gate dielectric, the AlGaN/GaN MISHEMT with a 2 μm-gate-length shows a high on/off ratio of 2.59 × 108 and a low subthreshold slope (SS) of 84 mV dec−1 among all GaN MISHEMTs using TiO2 as the gate dielectric. This work provides a feasible way to significantly improve the TiO2 film electrical property for gate dielectrics, and it suggests that the developed TiO2 dielectric is a promising high-κ gate oxide and a potential passivation layer for GaN-based MISHEMTs, which can be further extended to other transistors.

(Invited) Atomic-Scale Design of Advanced Transistors Via Ultrathin Negative Capacitance Gate Stacks

Negative capacitance [1,2] has emerged as a promising solution to overcome fundamental energy-efficiency limits in conventional electronics, in which internal ferroelectric order within the gate stack of a field-effect transistor can enable low-power operation. Thus far, claims of negative capacitance have been primarily demonstrated in perovskite-structure thick films or through misleading “S-curve” transient experiments in fluorite-structure thick films. However, integration into advanced semiconductor technology nodes will require stabilization at the ultrathin regime and evidence of capacitance enhancement (i.e. lower equivalent oxide thickness, EOT) to enable highly-scaled lower-power operation.Here, we present evidence of negative capacitance in atomic-scale HfO2-ZrO2 heterostructures down to two-nanometers and one-nanometer thickness [3,4], leveraging our recent work examining the atomic limits of fluorite-structure ferroelectricity on silicon [5,6]. ALD HfO2-ZrO2-based heterostructures on Si-SiO2 demonstrate ultralow EOT without having to scavenge the SiO2 interlayer, in stark contrast to conventional high-κ metal gate (HKMG) technology [7]. Accordingly, in comparison to industrial HKMG benchmarks, these SiO2-buffered antiferroelectric-ferroelectric gate stacks boast favorable performance and can provide multiple node technology boosts [8]. Due to seamless integration and transition from high-κ HfO2-based dielectrics to negative-κ HfO2-ZrO2-based ferroelectrics, these NC stacks have already been validated and integrated by prototyping foundries [8] and semiconductor foundries [9].In this talk, key differences between static versus transient negative capacitance will be highlighted to clarify misleading literature and explain their relative benefits for logic transistors [3,4] versus other applications [10]. Perspectives on further routes to EOT scaling via negative capacitance gate stacks for beyond-1-nm-node logic technology will also be discussed. R Landauer. “Can capacitance be negative.” Collect. Phenom. 2, 167–170 (1976).S Salahuddin & S Datta. “Can the subthreshold swing in a classical FET be lowered below 60 mV/decade?” in 2008 IEEE International Electron Devices Meeting (IEEE, 2008).S Cheema et al. “Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors.” Nature 604, 65–71 (2022).S Cheema et al. “Physical and electric thickness limits of negative capacitance.” In preparation (2024).S Cheema et al. “Emergent ferroelectricity in subnanometer binary oxide films on silicon.” Science 376, 648–652 (2022).S Cheema et al.“Enhanced ferroelectricity in ultrathin films grown directly on silicon.” Nature 580, 478–482 (2020).T Ando “Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?” Materials 5, 478–500 (2012).N Shanker et al. “CMOS Demonstration of Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack in a Self-Aligned, Replacement Gate Process.” in 2022 International Electron Devices Meeting (IEDM) 34.3.1-34.3.4 (IEEE, 2022).S Jo. et al. “Negative differential capacitance in ultrathin ferroelectric hafnia.” Nat. Electron. 6, 390–397 (2023).S Cheema et al.“Giant energy storage and power density negative capacitance superlattices.” Nature doi:10.1038/s41586-024-07365-5 (2024).

(Invited) Applications of Oxygen Inserted Epitaxy

Silicon remains the semiconductor material of choice for most electronic applications of semiconductors and the silicon–silicon dioxide interface is one of the most studied interfaces. Over the past decade or more, epitaxial silicon-germanium (eSiGe) has found increasing applications in advanced logic, first for PMOS compressive source-drain (S/D) stressors, then as a channel material in high-k metal gate (HKMG) devices to help control the PMOS Vt, and more recently as a sacrificial layer to enable stacked nanosheets and even as a S/D liner to reduce phosphorus diffusion into the undoped nanosheets. Oxygen inserted (OI) silicon epitaxy was originally developed to complement and bridge the gap between silicon and silicon-germanium, and it has found applications ranging from improved figure of merit power devices to the most advanced nanosheet applications. In this paper we will provide an overview of OI silicon devices, their fundamental characterization and the electrical and physical benefits offered for a variety of semiconductor applications. Introduction Oxygen-inserted (OI) silicon had an unusual genesis for a semiconductor material, in that it was first explored using ab-initio quantum mechanical simulation. It was found that by carefully inserting a partial monolayer of oxygen during silicon epitaxy a stable layer could be manufactured where the individual oxygen atoms arranged themselves on a silicon-silicon bond, but that overall, the silicon retained its regular lattice, and the silicon-oxygen coordination was only one, as opposed to four in regular silicon dioxide. The idealized lattice configuration is shown in Fig. 1 (a). This configuration is technically thermodynamically metastable, but with a significant energetic barrier to formation of four-fold coordinated silicon dioxide, so that it can survive conventional semiconductor processing. Whereas a single oxygen atom is known to rapidly diffuse in silicon, there is a thermodynamic self-stabilization when the oxygen concentration has an aerial density of the order of 1E15cm-2, with an upper limit dependent both on the specific epitaxial recipe and the required defect density. If all available silicon bonds have attached oxygen, it is difficult to maintain high quality epitaxy. On the other hand, OI silicon has passed the most rigorous defect density requirements for advanced logic applications. Dopant engineering - simulation Oxygen is highly electronegative, and ab initio simulation shows that there is charge transfer in the silicon lattice in the near vicinity of the inserted oxygen as shown in Fig 1 (b). This leads to a change in the formation enthalpy for a single substitutional dopant atom or addition of a silicon point defect, vacancy or interstitial as shown in Fig 1 (c). The figure indicates that substitutional boron and phosphorus will have an energetic preference to be two or three silicon lattice atoms away from the inserted oxygen, whereas silicon point defects prefer to be coincident with the oxygen. As a result, the OI layers disrupt the diffusion of dopant-interstitial pairs, substantially reducing the dopant diffusion. Dopant engineering – experimental data OI silicon has been proven to create unique abrupt doping profiles for a variety of silicon and silicon germanium devices. In power devices, reducing the vertical and lateral diffusion below the OI silicon layer can be used to engineer significant improvement in critical figures of merit, such as the tradeoff between specific ON resistance (Rsp) and the breakdown voltage, and improved time constant (Ron∙ Coff) and reduced body current in RF power devices, while maintaining breakdown voltage. In advanced 3D applications, a 2nm thin liner of OI silicon has proven effective to create a diffusion barrier between highly doped epitaxial source/drain regions and undoped channels. By reducing dopant up-diffusion, thermally robust super-steep retrograde profiles can be created, which can be used to reduce local threshold voltage mismatch in both NMOS and PMOS devices by more than 50%. In gate-first HKMG planar CMOS applications, SiGe channel is used in the PMOS to facilitate Vt engineering. A thin OI silicon layer below the SiGe channel can be used to maintain a super-steep retrograde channel profile after HKMG formation and subsequent thermal processing. Interface interactions It has recently been discovered that OI silicon can also be used to engineer adjacent interfaces. For example, it has been shown by cryogenic measurements that OI silicon reduces surface roughness scattering of the silicon-dielectric interface. Also, OI silicon can reduce the interfacial dipole formed during HKMG processing, with benefits in reduced remote charge scattering and improved reliability.These and other examples of engineered silicon and silicon-germanium devices will be discussed in detail. Figure 1

(Invited) Interface Control Process of Rare-Earth Oxides on Si for Gate Dielectric Application

High-k gate dielectrics are indispensable to overcome the shot-channel effect in scaled CMOS devices [1]. Besides the enhanced electrostatic control of the gate electrode, high-k/Si interface properties, including interface state density, fixed charges, dipoles, carrier mobility, reliability, and so on, need to meet the requirement levels. Rare earth oxides have been intensively studied for gate dielectric applications as these oxides react with Si to form a silicate layer, whereas, for the HfO2 case, a SiO2-based low-k interface layer is formed. One of the issues for rare earth oxide gate dielectrics is controlling the reaction amount while obtaining a good interface property. In this presentation, the interface reaction of rare-earth oxides and Si is modeled and controlled by the thermal treatment process. Furthermore, the influence of the metal gate electrode on the interface is assessed. A la-silicate interface layer is formed between the La2O3 film and Si interface. Although the La atom content in the reactively formed silicate layer generally depends on the annealing environment, a silicate/Si interface can be easily formed, which is advantageous for gate dielectric scaling. However, even under the same process, the La atom content in the silicate increases with the thinning of the initial La2O3 thickness, and the interface state density, flat-band voltage, and mobility degrade [2]. The reaction between La2O3 and Si can be modeled by oxygen atom supply from the environment, and the influence of the metal gate can explain the degradation of electrical properties. A La-rich silicate can be formed with nice interface properties by controlling the supplied oxygen atoms by selecting a proper metal gate stack [3]. The crystal grain size in the metal gate also affects the interface state density. A low interface state density can be obtained by adopting a metal gate material with nano-sized grains [4].In conclusion, an interface control process of La2O3 film on Si is presented by limiting the oxygen atom supply during the interface reaction. La-rich silicate, a high-k film, can be obtained by adopting a proper stacked gate structure. Also, nano-sized grains in the metal electrodes can exhibit a decent interface property.[1] J. Robertson, et al., Materials Science and Engineering R, 88, 1 (2015).[2] K. Kakushima, et al., Solid-State Electron., 54, 715 (2010).[3] T. Kawanago, et al., IEEE Trans. on ED, 59, 269 (2011).[4] K. Tuokedaerhan, et al., Appl. Phys. Lett., 104, 021601 (2014).

All Solution-Processed High-Performance MoS2 Thin Film Transistors with the High-k Perovskite Oxide Dielectric

Solution-processable van der Waals (vdW) materials with atomic layered crystal structures, are increasingly recognized as promising components for emerging electronic device applications. These materials offer exceptional quality and stability, coupled with the advantage of large-scale and low-temperature processability. Among these, van der Waals-assembled thin films made from transition metal dichalcogenides in solution have recently emerged as highly potential candidates for fabricating high-performance thin-film transistors (TFTs). Despite recent progress, fully solution-processed vdW electronics remain elusive, primarily due to the absence of suitable dielectric materials and scalable fabrication methodologies. In this report, we introduce the all solution-processed MoS2 TFTs, incorporating perovskite oxides as high-k gate dielectrics. The fabrication process involves preparing colloidal inks for each constituent layer through chemical or electrochemical exfoliation methods, followed by sequential assembly processes forming the semiconductor/dielectric heterostructure. All fabrication steps are performed at temperatures below 250 ℃. The resulting MoS2 TFTs, utilizing Dion-Jacobson-phase perovskite as the dielectric layer, demonstrate superior device characteristics. Notably, they exhibit an ON/OFF ratio exceeding 106, including high mobility (>10 cm2 V-1s-1). Additionally, the integration of high-k dielectric materials enables the transistors to operate at low leakage current (~10-11 A) and very low voltages, around approximately 5 V, significantly reducing power consumption. These TFTs are also compatible with flexible substrates, which further demonstrates their robustness and adaptability in a variety of electronic applications. The successful demonstration of low-temperature fabrication techniques for high-performance MoS2 TFTs not only marks a significant advancement in the field of solution-processable electronic devices but also paves the way for cost-effective, scalable electronics that are capable of hetero-integration.

Device to circuit level implementation of JL-NSFET for DC/analog/RF applications at sub-5nm technology node: design optimization and temperature analysis

Abstract This manuscript introduces, for the first time, a novel approach that incorporates a comprehensive analysis of sheet variations (1–5) and every individual sheet wise temperature variation, and as well as an investigation of various GS high-k gate dielectrics in Junction-less (JL) Nanosheet FET (JL-NSFET). The study starting from device level (Digital/Analog/Radio Frequency) to circuit (CMOS Inverter and ring oscillator) as a whole package is investigated through well calibrated TCAD simulation and the results portrayed. NSFETs are the ultimate choice for integrated circuits (ICs) at sub-5 nm technology node. The notion of this paper is to design and optimization of NSFET with GS high-k gate dielectrics (Al2O3, HfO2, ZrO2 and TiO2) Initially. The switching/analog and RF metric revels that HfO2 is superior in terms SS, switching applications and more compactable with CMOS process. Further, adding number of sheets and temperature variation has been done later. As number of sheets increases, the effective channel width increases, electric field distribution takes place evenly and enhanced gate control owing to improved I O N , I O N / I O F F r a t i o , SS and DIBL. However, increasing the number of vertical channel layers (sheets) more than 2 results into diminished analog/RF performance of JL-NSFET owing to increased parasitic capacitances. Further, the impact of temperature variations (250 K to 450 K) studied for different sheet variations (1 to 5) and noticed that analog/RF such as gm, gds, fT, TFP and GTFP are enhanced by 40.82%, 28.76%, 40.69%, 64.62% and 70.59%, respectively at lower temperature (250 K) when compared to high temperature (450 K). These enhancements make the device is ideal for applications in cryogenic computing systems, satellites, deep space probes, and other aerospace technologies. Furthermore, as the circuit level implementation CMOS inverter and 5-stage ring oscillator (RO) are examined for different sheets and observed as sheets increase delay and EDP increases. For a CMOS inverter the NMH (0.295 V) and NML (0.280 V) are better at 2 sheets with a highest gain of 9.38 V/V. Hence, it is advised to use two or three sheets-based JL-NSFETs for high-performance and lower-power analog/RF applications.

Numerical simulation of core shell dual metal gate stack junctionless accumulation mode nanowire FET (CS-DM-GS-JAMNWFET) for low power digital applications

In this paper, Core Shell Dual Metal Gate Stack Junctionless Accumulation Mode Nanowire FET (CS-DM-GS-JAMNWFET) is proposed, which has enhanced performance and is suitable for analog and digital applications. A high-k gate stack engineering, Hafnium Oxide (HfO2) is deployed in the outer as well as inner gate oxides of the core shell structure. The proposed device is compared with CS-DM-JAMNWFET, CS-SM-JAMNWFET, DM-GS-JAMNWFET, DM-JAMNWFET, and SM-JAMNWFET by maintaining a constant threshold voltage for all structures. The proposed CS-DM-GS-JAMNWFET provides a substantial reduction in subthreshold current with a high Ion/Ioff ratio as compared to other competent device structures. Also, the proposed device exhibits improvements in various parameters compared to the SM-JAMNWFET. It shows improvement in drain current (2.27 times), output conductance (2.14 times), subthreshold swing (0.94 times), transconductance (2.47 times), gate capacitance (2.00 times), cut-off frequency (1.24 times), intrinsic gain (12.95 times), current gain (1.46), Ion/Ioff ratio (6.15 times), unilateral power gain (1.09 times), maximum transducer power gain (1.08 times), Transconductance Generation factor (1.08 times), gain frequency product (14.61 times), transconductance frequency product (1.32 times), and gain transconductance frequency product (17.27 times). These benefits are due to combined advantages of the dual metal high-k dielectric HfO2 structure in core shell JAM FET, which enhances the device's gate dominance over the channel with high driving current.

Evaluating the performance of triple and double metal gate charge plasma transistors for applications in biological sensors at a dual cavity location

BackgroundBiosensors have become essential tools in biotechnology, environmental monitoring, and healthcare industries due to their ability to detect and analyze biological signals. However, conventional Tunnel Field-Effect Transistors (TFETs) used in biosensors face challenges like reduced ON-state current, random dopant fluctuations, and complex manufacturing processes, which limit their effectiveness. AimThe study aims to investigate the effectiveness of Charge Plasma-based Tunnel Field-Effect Transistors (CP-TFETs) with dual and triple metal gate-dual cavity locations for improving the sensitivity and performance of biosensors. MethodologyThe study compares dual and triple metal gate CP-TFET configurations for signal amplification and detection in biosensors. The CP-TFETs use high-k gate dielectric materials to enhance ON-state current and reduce OFF-state current, while the impact of neutralized and charged substances in the cavities on surface energy, electric field, and energy bands is analyzed. ResultsThe triple metal gate configuration demonstrated superior sensitivity in detecting biomolecules compared to the dual metal gate. By utilizing high-k materials and optimizing the gate work function, the triple metal gate approach achieved higher drain current and reduced OFF-state current, leading to improved overall performance. ConclusionThe triple metal gate CP-TFET outperforms its dual metal counterpart in biosensor applications, offering higher sensitivity, increased ON-state current, and improved detection capabilities, making it a promising approach for enhancing biosensor effectiveness.

Investigation of the Electrical Characteristics of AlGaN/AlN/GaN Heterostructure MOS-HEMTs with TiO2 High-k Gate Insulator

This paper investigates the impact of TiO2 high-k gate insulator on the electrical characteristics of AlGaN/AlN/GaN MOS-HEMT transistors using MATLAB and Atlas-TCAD simulation software. The physical analytical model of the MOS-HEMTs is used for simulation from Al2O3, HfO2, and TiO2 as the gate dielectric materials, which provide higher performance and reliability of the MOS-HEMT devices. The device shows a good improvement in its result of the DC and AC characteristics with different permittivity of insulator materials. Thus, the DC and AC performance of GaN MOS-HEMTs is higher than with other insulators, such as Al2O3 and HfO2 by using TiO2 as the gate dielectric. Moreover, the simulation results proved that TiO2 is the better gate dielectric material to enhance the electrical reliability of the power switching devices for high-temperature applications such as electric automobiles.

Magnesium niobate as a high-κ gate dielectric for two-dimensional electronics

Magnesium niobate as a high-κ gate dielectric for two-dimensional electronics

Liquid Metal Oxide-Assisted Integration of High-k Dielectrics and Metal Contacts for Two-Dimensional Electronics.

Two-dimensional van der Waals semiconductors are promising for future nanoelectronics. However, integrating high-k gate dielectrics for device applications is challenging as the inert van der Waals material surfaces hinder uniform dielectric growth. Here, we report a liquid metal oxide-assisted approach to integrate ultrathin, high-k HfO2 dielectric on 2D semiconductors with atomically smooth interfaces. Using this approach, we fabricated 2D WS2 top-gated transistors with subthreshold swings down to 74.5 mV/dec, gate leakage current density below 10-6 A/cm2, and negligible hysteresis. We further demonstrate a one-step van der Waals integration of contacts and dielectrics on graphene. This can offer a scalable approach toward integrating entire prefabricated device stack arrays with 2D materials. Our work provides a scalable solution to address the crucial dielectric engineering challenge for 2D semiconductor-based electronics.

Ultraflat single-crystal hexagonal boron nitride for wafer-scale integration of a 2D-compatible high-κ metal gate.

Hexagonal boron nitride (hBN) has emerged as a promising protection layer for dielectric integration in the next-generation large-scale integrated electronics. Although numerous efforts have been devoted to growing single-crystal hBN film, wafer-scale ultraflat hBN has still not been achieved. Here, we report the epitaxial growth of 4 in. ultraflat single-crystal hBN on Cu0.8Ni0.2(111)/sapphire wafers. The strong coupling between hBN and Cu0.8Ni0.2(111) suppresses the formation of wrinkles and ensures the seamless stitching of parallelly aligned hBN domains, resulting in an ultraflat single-crystal hBN film on a wafer scale. Using the ultraflat hBN as a protective layer, we integrate the wafer-scale ultrathin high-κ dielectrics onto two-dimensional (2D) materials with a damage-free interface. The obtained hBN/HfO2 composite dielectric exhibits an ultralow current leakage (2.36 × 10-6 A cm-2) and an ultrathin equivalent oxide thickness of 0.52 nm, which meets the targets of the International Roadmap for Devices and Systems. Our findings pave the way to the synthesis of ultraflat 2D materials and integration of future 2D electronics.

Ab Initio Materials Modeling of Point Defects in a High-κ Metal Gate Stack of Scaled CMOS Devices: Variability Versus Engineering the Effective Work Function

Ab Initio Materials Modeling of Point Defects in a High-κ Metal Gate Stack of Scaled CMOS Devices: Variability Versus Engineering the Effective Work Function

Performance enhancement of 4H-SiC superjunction trench MOSFET with extended high-K dielectric

This paper proposes a 4H-SiC superjunction trench MOSFET with extended high-K dielectric under metal gate (EHK SJ-TMOS). The characteristics of EHK SJ-TMOS include the use of the high-K (HK) dielectric as the gate dielectric and the extension of the HK dielectric as a deep trench into the N-type drift region. The extended HK trench effectively modulates the electric field distribution in the SJ drift region, which improves the breakdown voltage (BV). The introduction of HK dielectric also assists in depleting the SJ drift region, which enables the drift region of EHK SJ-TMOS to use a higher doping concentration, thereby reducing Ron,sp. Furthermore, the application of high-K gate dielectric alleviates the high gate oxide electric field problem in conventional SiC superjunction trench MOSFETs (SiC SJ-TMOS). The simulation results demonstrate that EHK SJ-TMOS exhibits a 59.2 % reduction in Ron,sp, a 2.4 % increase in BV, and a 156.5 % improvement in the FOM (FOM = BV2/Ron,sp) compared to the SiC SJ-TMOS, indicating enhanced performance.

Enhanced electrical performance in graphene field-effect transistors through post-annealing of high-k HfLaO gate dielectrics

High-k gate dielectrics have attracted a great deal of attention in the investigation of transistors due to their unique properties such as superior gate controllability. However, their integration into graphene field-effect transistors (GFETs) remains problematic and the physical mechanisms governing the performance of these devices are still not fully understood. In this study, the effects of post-annealing on GFETs utilizing the high-k HfLaO ternary oxide as the gate dielectric were comprehensively investigated. The HfLaO film was deposited on top of graphene by magnetron sputtering, and the device performance with various post-annealing temperatures was conducted. It was found that post-annealing temperature can effectively increase the dielectric constant through balancing the oxygen-vacancy defects and moisture absorption. Both the surface morphology of HfLaO and performance of GFETs were investigated, and the fabricated GFETs exhibit notable electrical performance enhancements. Specifically, GFETs with a 200 °C post-annealed HfLaO gate dielectric demonstrate the optimal device performance, featuring a minimal Dirac point voltage (VDirac) of 1.1 V and a minimal hysteresis (ΔVDirac) of 0.5 V. The extracted hole and electron mobilities are 4012 and 1366 cm2/V · s, respectively, nearly one order of magnitude higher than that of GFETs with as-deposited HfLaO. This work outperforms other existing GFETs utilizing high-k gate dielectric and chemical vapor deposition grown graphene in terms of both carrier mobility and on–off ratio. It is also noted that the excessive post-annealing temperature can negatively impact the GFET performance through introducing oxygen vacancies, increasing the surface roughness, lowering the breakdown voltage, and inducing recrystallization.

Modeling and Sensitivity Estimation of a Dual Cavity Source Pocket-Based Charge Plasma Tunneling FET for Label-Free Biological Molecule Detection

A dual-source cavity charge plasma tunneling FET (DSC-SP-CPTFET) with SiGe Pocket is proposed, and its effectiveness as a biological sensor for label-free detection is explored. The fabrication complexity and cost have been reduced by using the charge-plasma concept. For improved sensing, an etched nanocavity is added to the upper and lower of the source metal section. The high-k (HfO2) gate oxide and minimal energy gap (Si0.6Ge0.4) alloy with a 40% mole fraction improve the current sensitivity by enhancing the drain current gradient. The sensitivity of the suggested biological sensor is assessed here for several neutral biological molecules, such as Gelatin, Keratin, Biotin, and 3-Aminopropyl-Triethoxysilane (APTES). Deoxyribonucleic acid (DNA), a charged biological molecule, is also considered with varying positive and negative charge densities. The suggested biological sensor shows a (SIDS)max of 2.21 × 1010 and a Sratio of 3.11 × 109 for biological molecules with higher dielectric constant at room temperature. Different electrostatic performances are estimated in the ON state, including energy band, electron (e-) BTBT rate, electrical field, and IDS-VGS characteristics. In addition, the proposed biological sensor provides a much superior drain current sensitivity (SIDS), current ratio sensitivity (Sratio), and average SS sensitivity (SSS) performance in the presence of both charged and neutral biological molecules.

Retraction Note: Exploring High-Temperature Reliability of 4H-SiC MOSFETs: A Comparative Study of High-K Gate Dielectric Materials

Retraction Note: Exploring High-Temperature Reliability of 4H-SiC MOSFETs: A Comparative Study of High-K Gate Dielectric Materials

Performance assessment of InGaAs–SOI–FinFET for enhancing switching capability using high-k dielectric

In this work, a high-k In0.53Ga0.47As silicon-on-insulator FinFET (InGaAs–SOI–FinFET) is presented for high-switching and ultra-low power applications at 7 nm gate length. Indium Gallium Arsenide (InGaAs) is a compound semiconductor that has gained attention in the field of semiconductor devices, including FinFETs. The incorporation of InGaAs in proposed FinFETs introduces several advantages, making it an attractive material for certain applications. InGaAs–SOI–FinFET performance has been observed and found high electron mobility, improved On-Current performance (ION), drain current (IDS), transconductance (gm), energy bands, lower subthreshold swing (SS), electric field, surface potential, and better short-channel behaviour. All the results of InGaAs–SOI–FinFET have been simultaneously compared with SOI-FinFET and conventional FinFET (C-FinFET). Incorporating InGaAs in the channel with high-k gate material enhances the drain current by ⁓75% and ⁓77% in the proposed device compared to the other two counterparts. Owing to the higher drain current in the InGaAs–SOI–FinFET, other parameters have also been improved, which leads to higher performance applications.