High-k Dielectric Layer Research Articles

Direct-Written Silver Electrodes for All-Solution-Processed Low-Voltage Organic Thin Film Transistors Towards Flexible Electronics Applications

Recent progress inprinted electronics has offered the possibility of fabricatingvarious organic-based electronic devices,such as organic light-emitting diodes (OLEDs) and organic thin film transistors (OTFTs).As one of the important deposition methods inprinted electronics, an inkjet printing technique offers the deposition of solution-processable materials onto a variety of substrates using simpler fabrication steps at lower processing temperatures, which is suitable for flexible electronic applications. Despite being the leading choice in OTFT fabrication,the clogging issues that frequently occurred at the printhead nozzle havenot only limitedthe material selection but also restrained the efforts to bring organic electronic devices to the market. Apart from that, although remarkable progress has been made to enhance the performance of the OTFT, the high operating voltage resulting from the low gate capacitance density of the inorganic oxide-based dielectric layer remains a critical limitation that hinders the practical application of the OTFT. Hence, in this paper, we propose a simple solution-based method to develop a low-voltageOTFT. This work utilized a direct-write printing technique to print silver source/drain and gate electrodes incorporated into a bottomgate bottom contact OTFT structure, a spin-coating deposition method to deposit both small molecule TIPS-pentacene organic semiconducting layer and high-kPVA dielectric layer. Notably, the proposed OTFT achieved a micrometre channel length with a saturation mobility of 4.49 × 10-1cm2/Vs, a threshold voltage of -1.5V, an on/off current ratio of 108, and a subthreshold swing of 66.8mV/dec whilethe overall fabrication temperature and operating voltage arekept below 150 °Cand -15 V, respectively.The direct ink writing technology incorporated into the high-kdielectric layer provides a new strategy to fabricate organic-related components,particularly the OFTFs at lower manufacturing cost and temperature towardsflexible and low-operating voltage electronic devices.

The comprehensive study of hybrid dielectric layer adopted organic thin film transistors for low voltage operation

Organic electronics hold immense promise due to their flexibility, low-cost processing, and diverse applications. Despite tremendous progress, low-voltage operation has remained a significant hurdle, impacting device efficiency. Our investigation introduces a new class of low voltage driven pentacene transistors, featuring hybrid gate insulators composed of polymer buffer layer and oxygen-plasma reacted high-k metal oxides viz. AlOx, TiOx, and TaOx. We demonstrate that a combination of titanium dioxide (TiOx) as the high-k dielectric layer and poly vinyl phenol (PVP) as a buffer layer in organic thin-film transistors (OTFTs) achieves exceptional performance compared to aluminium oxide (AlOx) and tantalum oxide (TaOx). This innovative approach yields the notable field-effect mobility (1.5 cm2/Vs) and a commendable on/off ratio (3.4 × 104), surpassing devices fabricated with other high-k oxides. The success lies in the PVP’s ability to smooth surfaces and reduce interface defects, while TiOx’s superior dielectric constant fosters stronger gate control. These findings pave the way for the development of next-generation organic devices with significantly lower operating voltages, opening doors for energy-efficient and flexible electronics.

Analysis of breakdown voltage for GaN MIS-HEMT with various composite field plate configurations and passivation layers

The effects of different field plate designs on the breakdown voltage of GaN Metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) were examined in this study. The study's primary goal was to determine the dependence of breakdown voltage with respective to composite field plate designs using TCAD simulation. For devices featuring only G-FP, with a fixed gate to drain distance of 15 μm and a fixed G-FP to drain distance of 15 μm, the maximum breakdown voltage was achieved 1 μm G-FP. Breakdown voltage trends were also determined for composite field plate configurations, such as adding a source field plate (S-FP) or a drain field plate (D-FP) with a fixed 1 μm G-FP length. A further enhancement in device breakdown performance was demonstrated by employing a novel D-FP structure. A single D-FP improves the breakdown voltage from 1.4 kV (conventional breakdown voltage with 1um G-FP) to 1.6 kV when combined with 1 μm G-FP, while the novel two-step D-FP achieves a breakdown voltage of about 1.7 kV when combined with 1 μm G-FP. We also investigated the influence of high-k dielectric passivation layers on the breakdown voltage. The breakdown voltage of the devices with optimized G-FP can be further improved by using high-k dielectric material as a passivation layer. The thorough investigations contribute to a better understanding of GaN MIS-HEMT breakdown characteristics and prospective pathways for improving their performance via unique field plate designs and superior dielectric materials.

Surface engineering of high-k polymeric dielectric layers with a fluorinated organic crosslinker for use in flexible-platform electronics.

High-k polymeric layers were prepared by combining various functional groups and were applied as gate dielectrics for practical organic field-effect transistors (OFETs). Crosslinking of the polymeric layers through UV-assisted organic azide fluorine-based crosslinkers induced dramatic improvements in the electrical performance of the OFET, such as field-effect mobility and bias-stress stability. Our synthesis and manufacturing method can be a useful technique for ensuring device operation stability and electrical property enhancement. With this analysis, we further applied our polymer-dielectric OFETs to flexible-platform-based electronic components, including unit OFETs and simple logic devices (NOT, NAND, and NOR gates). The outcomes of this research and development suggest a suitable method for the low-cost mass production of large-area flexible and printable devices, using a printing-based approach to replace current processes.

Ultrathin Van der Waals Lanthanum Oxychloride Dielectric for 2D Field-Effect Transistors.

Downsizing silicon-based transistors can result in lower power consumption, faster speeds, and greater computational capacity, although it is accompanied by the appearance of short-channel effects. The integration of high-mobility 2D semiconductor channels with ultrathin high dielectric constant (high-κ) dielectric in transistors is expected to suppress the effect. Nevertheless, the absence of a high-κ dielectric layer featuring an atomically smooth surface devoid of dangling bonds poses a significant obstacle in the advancement of 2D electronics. Here, ultrathin van der Waals (vdW) lanthanum oxychloride (LaOCl) dielectrics are successfully synthesized by precisely controlling the growth kinetics. These dielectrics demonstrate an impressive high-κ value of 10.8 and exhibit a remarkable breakdown field strength (Ebd ) exceeding 10 MV cm-1 . Remarkably, the conventional molybdenum disulfide (MoS2 ) field-effect transistor (FET) featuring a dielectric made of LaOCl showcases an almost negligible hysteresis when compared to FETs employing alternative gate dielectrics. This can be attributed to the flawlessly formed vdW interface and excellent compatibility established between LaOCl and MoS2 . These findings will motivate the further exploration of rare-earth oxychlorides and the development of more-than-Moore nanoelectronic devices.

A Design of High-Efficiency: Vertical Accumulation Modulators Based on Silicon Photonics.

On-chip optical modulators, which are capable of converting electrical signals into optical signals, constitute the foundational components of photonic devices. Photonics modulators exhibiting high modulation efficiency and low insertion loss are highly sought after in numerous critical applications, such as optical phase steering, optical coherent imaging, and optical computing. This paper introduces a novel accumulation-type vertical modulator structure based on a silicon photonics platform. By incorporating a high-K dielectric layer of ZrO2, we have observed an increase in modulation efficiency while maintaining relatively low levels of modulation loss. Through meticulous study and optimization, the simulation results of the final device structure demonstrate a modulation efficiency of 0.16 V·cm, with a mere efficiency-loss product of 8.24 dB·V.

Impact on DC and analog/RF performances of SOI based GaN FinFET considering high-k gate oxide

This paper suggests an analysis of SOI-based GaN FinFET that considers high-k gate oxide into account. The effect of using SOI substrate and a high-k dielectric layer on ON current, OFF current, electric field, electron mobility, conduction & valence band energy, and subthreshold swing is reported. All these parameters are analyzed and compared with bulk GaN FinFET and Si FinFET. We achieve better ON current, faster speed, and more minor subthreshold swing, reducing the short channel effects. A shallow OFF current is obtained because of bulk conduction in the GaN channel area, which the gate can deplete. Several RF/analog metrics are also noted, including transconductance (gm), cut-off frequency (fT), transconductance frequency product (TFP), and transconductance generation factor (TGF), and comparison with Bulk GaN FinFET and Si FinFET is presented. Finally, the linearity metrics like 2nd and 3rd-order voltage intercept points, IIP3, and 1-dB compression point is extracted. Compared to the other two structures, the suggested structure exhibits advantageous DC and RF/analog performances. A comparison of different Figures of Merits (FoMs) for the suggested device with previously published literature is also given.

High-Performance Two-Dimensional Electronics with a Noncontact Remote Doping Method.

Because of the intrinsic low carrier density of monolayer two-dimensional (2D) materials, doping is crucial for the performance of underlap top-gated 2D devices. However, wet etching of a high-k (dielectric constant) dielectric layer is difficult to implement without causing performance deterioration on the devices; therefore, finding a suitable spacer doping technique for 2D devices is indispensable. In this study, we developed a remote doping (RD) method in which defective SiOx can remotely dope the underlying high-k capped 2D regions without directly contacting these materials. This method achieved a doping density as high as 1.4 × 1013 cm-2 without reducing the mobility of the doped materials; after 1 month, the doping concentration remained as high as 1.2 × 1013 cm-2. Defective SiOx can be used to dope most popular 2D transition-metal dichalcogenides. The low-k properties of SiOx render it ideal for spacer doping, which is very attractive from the perspective of circuit operation. In our experiments, MoS2 and WS2 underlap top-gate devices exhibited 10× and 200× increases in their on-currents, respectively, after being doped with SiOx. These results indicate that SiOx doping can be conducted to manufacture high-performance 2D devices.

Corona Poling Induced Phase Transition to Highly Polar Phase in P(VDF-TrFE-CFE) Dielectric and Charge Transport of Organic Field-Effect Transistors.

Increasing the number of charge carriers flowing through the charge transport channel to improve the electrical performance of organic field-effect transistors (OFETs) is important because it leads to a low driving voltage and a high drain current value. This paper proposes a new strategy, the corona poling process, to enhance the electrical performance of OFETs using an external electric field when forming a dielectric film using a PVDF-based high-k dielectric terpolymer, P(VDF-TrFE-CFE). A corona poling process was applied to align the dipoles with high-k dielectric molecules and improve the capacitance, thereby increasing the number of charge carriers. Through this process, by observing the phase transition of a PVDF dielectric through a corona poling process in the GIWAXS data, the phase transition through an external electric field was thoroughly revealed for the first time. As a result, the capacitance of high-k dielectric films can be improved, and the amount of charge carriers can be increased by a simple corona poling process. In addition, to reduce the effect of deep trap sites caused by the dipole alignment, a thin low-k dielectric, polystyrene (PS), was introduced between the active and high-k dielectric layers to provide trap site passivation, thereby increasing the electrical performance of the OFET. Therefore, through this strategy, using a diketopyrrolopyrrole (DPP)-based donor-acceptor (D-A) copolymer as an active material of OFET, the average saturation region hole mobility was improved from 0.34 to 0.60 cm2/Vs. Thus, the electrical performances of the OFETs were improved by enhancing the capacitance through the corona poling process and reducing the charge carrier trap sites introduced by the high-k and low-k bi-layer dielectric layer. Importantly, this work offers a new strategy for the post-treatment to improve electrical performance of organic devices.

High-Performance Graphene Nanowalls/Si Self-Powered Photodetectors with HfO2 as an Interfacial Layer.

Graphene/silicon (Si) heterojunction photodetectors are widely studied in detecting of optical signals from near-infrared to visible light. However, the performance of graphene/Si photodetectors is limited by defects created in the growth process and surface recombination at the interface. Herein, a remote plasma-enhanced chemical vapor deposition is introduced to directly grow graphene nanowalls (GNWs) at a low power of 300 W, which can effectively improve the growth rate and reduce defects. Moreover, hafnium oxide (HfO2) with thicknesses ranging from 1 to 5 nm grown by atomic layer deposition has been employed as an interfacial layer for the GNWs/Si heterojunction photodetector. It is shown that the high-k dielectric layer of HfO2 acts as an electron-blocking and hole transport layer, which minimizes the recombination and reduces the dark current. At an optimized thickness of 3 nm HfO2, a low dark current of 3.85 × 10-10, with a responsivity of 0.19 AW-1, a specific detectivity of 1.38 × 1012 as well as an external quantum efficiency of 47.1% at zero bias, can be obtained for the fabricated GNWs/HfO2/Si photodetector. This work demonstrates a universal strategy to fabricate high-performance graphene/Si photodetectors.

Intercalation of hafnium oxide between epitaxially-grown monolayer graphene and Ir(111) substrate

Intercalation of insulating materials between epitaxial graphene and the metal substrates is highly demanded to restore the intrinsic properties of graphene, and thus essential for the graphene-based devices. Here we demonstrate a successful solution for the intercalation of hafnium oxide into the interface between full-layer graphene and Ir(111) substrate. We first intercalate hafnium atoms beneath the epitaxial graphene. The intercalation of the hafnium atoms leads to the variation of the graphene moiré superstructure periodicity, which is characterized by low-energy electron diffraction (LEED) and low-temperature scanning tunneling microscopy (LT-STM). Subsequently, we introduce oxygen into the interface, resulting in oxidization of the intercalated hafnium. STM and Raman’s characterizations reveal that the intercalated hafnium oxide layer could effectively decouple the graphene from the metallic substrate, while the graphene maintains its high quality. Our work suggests a high-k dielectric layer has been successfully intercalated between high-quality epitaxial graphene and metal substrate, providing a platform for applications of large-scale, high-quality graphene for electronic devices.

Optically Controllable Organic Logic-in-Memory: An Innovative Approach toward Ternary Data Processing and Storage.

Logic-in-memory (LIM) has emerged as an energy-efficient computing technology, as it integrates logic and memory operations in a single device architecture. Herein, a concept of ternary LIM is established. First, a p-type 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) transistor is combined with an n-type PhC2H4-benzo[de]isoquinolino[1,8-gh]quinolone diimide (PhC2-BQQDI) transistor to obtain a binary memory inverter, in which a zinc phthalocyanine-cored polystyrene (ZnPc-PS4) layer serves as a floating gate. The contrasting photoresponse of the transistors toward visible and ultraviolet light and the efficient hole-trapping ability of ZnPc-PS4 enable us to achieve an optically controllable memory operation with a high memory window of 18 V. Then, a ternary memory inverter is developed using an anti-ambipolar transistor to achieve a three-level data processing and storage system for more advanced LIM applications. Finally, low-voltage operation of the devices is achieved by employing a high-k dielectric layer, which highlights the potential of the developed LIM units for next-generation low-power electronics.

Dielectric loss reduction and validation of P(VDF-HFP) films via sandwiching film fabrication for capacitive energy storage

Poly(vinylidene fluoride) (PVDF) series polymers have a high dielectric constant (k) among polymer families but a high intrinsic loss tangent disqualifying their capacitor application. In this work, Poly(vinylidene fluoride-hexafluoropropylene) (P(VDF-HFP)) copolymer as the high-k dielectric layer is sandwiched between two low-k polyetherimide (PEI and PEI/BaTiO3) layers to construct the composite films with tunable dielectric responses. By changing the low-k layer thickness in the PEI/P(VDF-HFP)/PEI tri-layer structure, its characteristic of capacitors in series results in the moderate dielectric constant and dramatic reduction of loss tangent to a meaningful level for capacitor design. The loss tangent can be dramatically reduced to below 0.005 at 1 kHz using the thickness ratio of 1:1:1 from about 0.03 for P(VDF-HFP) film alone. The extraordinary dielectric response of the tri-layer structure is also accompanied by more than 2 times the higher energy density than that of the PEI film under the same electric field. The ingenious design of the low-k/high-k/low-k sandwiched polymers synergizes the high-k advantage of P(VDF-HFP) and low tangent loss of the low-k layer as well as their high dielectric strength. This work provides a meaningful and effective method for realizing PVDF-based polymers with reduced loss tangent for actual capacitor application.

All inkjet-printed electronics based on electrochemically exfoliated two-dimensional metal, semiconductor, and dielectric

Inkjet printing is a cost-effective and scalable way to assemble colloidal materials into desired patterns in a vacuum- and lithography-free manner. Two-dimensional (2D) nanosheets are a promising material category for printed electronics because of their compatibility with solution processing for stable ink formulations as well as a wide range of electronic types from metal, semiconductor to insulator. Furthermore, their dangling bond-free surface enables atomically thin, electronically-active thin films with van der Waals contacts which significantly reduce the junction resistance. Here, we demonstrate all inkjet-printed thin-film transistors consisting of electrochemically exfoliated graphene, MoS2, and HfO2 as metallic electrodes, a semiconducting channel, and a high-k dielectric layer, respectively. In particular, the HfO2 dielectric layer is prepared via two-step; electrochemical exfoliation of semiconducting HfS2 followed by a thermal oxidation process to overcome the incompatibility of electrochemical exfoliation with insulating crystals. Consequently, all inkjet-printed 2D nanosheets with various electronic types enable high-performance, thin-film transistors which demonstrate field-effect mobilities and current on/off ratios of ~10 cm2 V−1 s−1 and >105, respectively, at low operating voltage.

Design optimization of high breakdown voltage vertical GaN junction barrier Schottky diode with high-K/low-K compound dielectric structure

A vertical junction barrier Schottky diode with a high-K/low-K compound dielectric structure is proposed and optimized to achieve a high breakdown voltage (BV). There is a discontinuity of the electric field at the interface of high-K and low-K layers due to the different dielectric constants of high-K and low-K dielectric layers. A new electric field peak is introduced in the n-type drift region of junction barrier Schottky diode (JBS), so the distribution of electric field in JBS becomes more uniform. At the same time, the effect of electric-power line concentration at the p–n junction interface is suppressed due to the effects of the high-K dielectric layer and an enhancement of breakdown voltage can be achieved. Numerical simulations demonstrate that GaN JBS with a specific on-resistance (R on,sp) of 2.07 mΩ⋅cm2 and a BV of 4171 V which is 167% higher than the breakdown voltage of the common structure, resulting in a high figure-of-merit (FOM) of 8.6 GW/cm2, and a low turn-on voltage of 0.6 V.

Lg = 50 nm Gate-All-Around In0.53Ga0.47As Nanosheet MOSFETs with Regrown In0.53Ga0.47As Contacts

In this paper, we report the fabrication and characterization of Lg = 50 nm Gate-All-Around (GAA) In0.53Ga0.47As nanosheet (NS) metal-oxide-semiconductor field-effect transistors (MOSFETs) with sub-20 nm nanosheet thickness that were fabricated through an S/D regrowth process. The fabricated GAA In0.53Ga0.47As NS MOSFETs feature a bi-layer high-k dielectric layer of Al2O3/HfO2, together with an ALD-grown TiN metal-gate in a cross-coupled manner. The device with Lg = 50 nm, WNS = 200 nm and tNS = 10 nm exhibited an excellent combination of subthreshold-swing behavior (S < 80 mV/dec.) and carrier transport properties (gm_max = 1.86 mS/μm and ION = 0.4 mA/μm) at VDS = 0.5 V. To the best of our knowledge, this is the first demonstration of InxGa1-xAs GAA NS MOSFETs that would be directly applicable for their use in future multi-bridged channel (MBC) devices.

Impact of channel parameters on threshold voltage at variable temperatures of Double-gate CNTFET

This paper focuses mainly on the effect of various channel parameters like chirality, diameter of CNT, high-k dielectric materials and oxide layer thickness of DG-CNTFET on the threshold voltage at different temperature range of 225K–400K using nanoHUB simulation tools. The minor reductions (less than 5%) in threshold voltage of DG-CNTFET with respect to variable temperature increasing from 225K to 400K are observed. The results show that the threshold voltage increases with the reduction in carbon nanotube diameter of DG-CNTFET which affects the thermal conductivity of device as the van der Waals interaction between carbon-carbon bonds gets affected in DG-CNTFET. It was also investigated that decrease in quantum capacitance of DG-CNTFET improves the propagation delay of device. Using higher k-dielectric materials in DG-CNTFET enables faster switching speeds and lowers the power dissipation. Finally, based on results a conclusion has been drawn that best performance was recorded at lower value of temperature for threshold voltage.

Engineering Top Gate Stack for Wafer-Scale Integrated Circuit Fabrication Based on Two-Dimensional Semiconductors.

In recent years, two-dimensional (2D) semiconductors have attracted considerable attention from both academic and industrial communities. Recent research has begun transforming from constructing basic field-effect transistors (FETs) into designing functional circuits. However, device processing remains a bottleneck in circuit-level integration. In this work, a non-destructive doping strategy is proposed to modulate precisely the threshold voltage (VTH) of MoS2-FETs in a wafer scale. By inserting an Al interlayer with a varied thickness between the high-k dielectric and the Au top gate (TG), the doping could be controlled. The full oxidation of the Al interlayer generates a surplus of oxygen vacancy (Vo) in the high-k dielectric layer, which further leads to stable electron doping. The proposed strategy is then used to optimize an inverter circuit by matching the electrical properties of the load and driver transistors. Furthermore, the doping strategy is used to fabricate digital logic blocks with desired logic functions, which indicates its potential to fabricate fully integrated multistage logic circuits based on wafer-scale 2D semiconductors.

In situ isotope study of indium diffusion in InP/Al2O3 stacks

A high-quality interface of III–V/high-k dielectrics is critical to obtain high-performance devices. Indium out-diffusion in an InP-based stack is correlated with the density of interface states. Diffused In species are in the form of oxides, which invite the question about the diffusion of species through the high-k dielectric layer. For an InP/Al2O3 stack, O18 isotope tracing is carried out to investigate if the interface oxygen and indium atoms diffuse together or not. This work sheds light on the fundamental mechanism for III–V semiconductors' interface elemental diffusion as well as the interface passivation strategy.

Sol-Gel Composites-Based Flexible and Transparent Amorphous Indium Gallium Zinc Oxide Thin-Film Synaptic Transistors for Wearable Intelligent Electronics

In this study, we propose the fabrication of sol-gel composite-based flexible and transparent synaptic transistors on polyimide (PI) substrates. Because a low thermal budget process is essential for the implementation of high-performance synaptic transistors on flexible PI substrates, microwave annealing (MWA) as a heat treatment process suitable for thermally vulnerable substrates was employed and compared to conventional thermal annealing (CTA). In addition, a solution-processed wide-bandgap amorphous In-Ga-Zn (2:1:1) oxide (a-IGZO) channel, an organic polymer chitosan electrolyte-based electric double layer (EDL), and a high-k Ta2O5 thin-film dielectric layer were applied to achieve high flexibility and transparency. The essential synaptic plasticity of the flexible and transparent synaptic transistors fabricated with the MWA process was demonstrated by single spike, paired-pulse facilitation, multi-spike facilitation excitatory post-synaptic current (EPSC), and three-cycle evaluation of potentiation and depression behaviors. Furthermore, we verified the mechanical robustness of the fabricated device through repeated bending tests and demonstrated that the electrical properties were stably maintained. As a result, the proposed sol-gel composite-based synaptic transistors are expected to serve as transparent and flexible intelligent electronic devices capable of stable neural operation.