High-k Dielectric Applications Research Articles

High permittivity SrHf0.5Ti0.5O3 films grown by pulsed laser deposition

High permittivity SrHf0.5Ti0.5O3 films (k=62.8) have been deposited on (001) Nb–SrTiO3 single crystal conducting substrates by pulsed laser deposition. The SrHf0.5Ti0.5O3 films grow epitaxially with atomically smooth surfaces (root mean square roughness 4.8 Å) and a c-axis orientation parallel to the substrate. The measured band gap of SrHf0.5Ti0.5O3 is 3.47 eV compared with 3.15 eV in SrTiO3. Under an applied electric field of 600 kV/cm, the leakage current density of the SrHf0.5Ti0.5O3 films is 4.63×10−4 A/cm2. These attractive dielectric properties and enhanced band gap values make SrHf0.5Ti0.5O3 a promising candidate for high-k dielectric applications in silicon-based integrated circuits.

MOSFET characteristics with poly-Si/HfAlON gate stacks using ultra-thin UV-ozone interfacial oxide

This paper conducts a comprehensive evaluation of the electrical characteristics of the poly-silicon gated n-channel metal–oxide–semiconductor field-effect-transistor (nMOSFET) with hafnium–aluminum-oxynitride (HfAlON) gate dielectric with interfacial ultraviolet-ozone (UV-O 3) oxide or chemical oxide. Interfacial UV-O 3 oxide exhibits well-controlled interfacial properties due to self-saturated growth and thick-oxide-comparable density, which is beneficial to suppress interfacial re-oxidation and reduces surface roughness. Compared with interfacial chemical oxide, the interfacial UV-O 3 oxide obviously improves both gate insulating and interface characteristics, including breakdown voltage increments, reduced gate leakage current, and as-deposited traps. In addition, the HfAlON gate stack with UV-O 3 interface oxide also shows encouraging nMOSFET device performances, with a small subthreshold swing, high electron mobility, saturation drain current, and negligible stress-induced trap generation. The results clearly suggest that the high-density interfacial UV-O 3 oxide possess a high potential to be integrated with further high-k dielectric applications.

Suppression of parasitic electron injection in silicon-oxide-nitride-oxide-silicon-type memory cells using high-k capping layers

In this article the application of thin high-k dielectrics as capping layers on oxide/nitride/oxide memory stacks with respect to suppression of electron injection from the gate electrode during erase operation is investigated. The authors demonstrate that hafnium silicate layers, with a dielectric constant of 17, as thin as 1nm of physical thickness can clearly reduce electron injection and thereby prevent erase saturation. In theory, tunneling currents will be more strongly suppressed with increasing k values when keeping the equivalent oxide thickness constant. Therefore, the prevention of erase saturation will be further improved. However, titanium oxide as capping layer, which has a dielectric constant of 60, exhibits inferior erase performance due to a strong electron injection by field-enhanced thermal emission of electrons. This Poole-Frenkel conduction mechanism takes place along trapping sites 0.32eV below the conduction band in the titanium dioxide. While the application of high-k materials can efficiently suppress erase saturation due to tunneling currents, this effect can be diminished by leakage currents along shallow trapping sites which occur in high-k dielectrics.

SrTa 2 O 6 thin films for high-K dielectric applications grown by chemical vapor deposition on different substrates

SrTa 2 O 6 thin films with thickness between 6 and 150 nm were deposited by metal-organic chemical vapor deposition in a multiwafer planetary reactor. The monomolecular precursor, strontium-tantalum-(methoxyethoxy)-ethoxide, was dissolved in toluene and injected by a liquid delivery system. A rather narrow process window for the deposition of stoichiometric SrTa2O6 was found for this precursor at low pressures and a susceptor temperature around 500 °C. Films were grown on Pt∕TiO2∕SiO2∕Si, TiNx∕Si, and SiO2∕Si substrates. The as-deposited films were x-ray amorphous and could be crystallized by postannealing at a temperature ⩾700°C. The distorted tetragonal tungsten bronze phase of SrTa2O6 was dominating within a broad range of compositions (Sr∕Ta: 0.4–0.7) and a perovskite-type phase was additionally observed for Sr∕Ta>0.7 and predominated for Sr∕Ta>1. The electrical properties have been investigated with metal-insulator-metal and metal-insulator-semiconductor capacitors after sputter deposition of Pt top electrodes. The amorphous films had a dielectric constant K in the range of 35–45 and low leakage currents. For stoichiometric SrTa2O6 the dielectric permittivity reached values of K=100–110, but the leakage currents were increased. Remarkably, the permittivity is not very sensitive to deviations from the exact stoichiometry of the SrTa2O6 phase (Sr∕Ta: 0.4–0.7), but a decrease to values of K=30–40 is observed along with the transition to the perovskite phase at high Sr contents.

Comparison of precursors for pulsed metal–organic chemical vapor deposition of HfO2 high-K dielectric thin films

Hafnium oxide films were deposited on Si(100) substrates using pulsed metal–organic chemical vapor deposition (CVD) and evaluated for high-K dielectric applications. Three types of precursors were tested: two oxygenated ones, Hf butoxide-dmae and Hf butoxide-mmp, and an oxygen-free one, Hf diethyl-amide. Depositions were carried out in the temperature range of 350–650 °C, yielding different microstructures ranging from amorphous to crystalline, monoclinic, films. The films were compared on the basis of growth rate, phase development, density, interface characteristics, and electrical properties. Some specific features of the pulsed injection technique are considered. For low deposition temperatures the growth rate for the amide precursor was significantly higher than for the mixed butoxide precursors. A thickness-dependent amorphous to crystalline phase transition temperature was found for all precursors. There is an increase of the film density along with the deposition temperature from values as low as 5 g/cm3 at 350 °C to values close to the bulk value of 9.7 g/cm3 at 550 °C. Crystallization is observed in the same temperature range for films of typically 10–20 nm thickness. However, annealing studies show that this density increase is not simply related to the crystallization of the films. Similar electrical properties could be observed for all precursors and the dielectric constant of the films reaches values similar to the best values reported for bulk crystalline HfO2.

A Universal Thermal Module™ for Clusterable RTP and MOCVD Applications

AbstractA Universal Thermal Module™ (UTM™) has been developed for vacuum-integrated cluster RTP and MOCVD as well as stand-alone atmospheric RTP applications. The UTM™ architecture provides highly modular RTP and MOCVD tool configurations for various single-wafer thermal processes. The UTM™ design comprises a temperature-controlled UHV-grade process chamber as well as an ultraclean gearless wafer rotation assembly for improved temperature uniformity and enhanced built-in reliability. The UTM™ RTP employs bottom/backside wafer heating using a multi-zone axisymmetric illuminator and a reflective multi-zone gas showerhead located above the wafer. Precision RTP control is achieved using a multi-zone controller in conjunction with a multipoint sensor system with real-time multi-zone compensations for wafer emissivity and illuminator light interference effects. The RTP temperature measurement and control techniques fully compensate for any axisymmetric or non-axisymmetric wafer emissivity patterns, eliminating the need for pre-RTP wafer backside conditioning. The UTM™ showerhead provides capabilities for ultraclean multi-zone gas injection and in-situ RF plasma for MOCVD and RTCVD processes. The UTM™ MOCVD module meets the most stringent specifications and tool parameters for various metallization and high-K dielectric deposition applications. This module has been used for deposition of low-resistivity copper films with excellent void-free sub-half-micron gap fill for high-performance multilevel interconnects. The UTM™ RTP and MOCVD modules have been implemented based on design optimizations in a virtual reactor environment.

Field effect transistor microwave characterization: noise figure, gain, power measurements on microwave bench: M. Binet and P. Baudet. Acta Electronica23 (2), 127 (1980) (in German)

A novel idea that using dynamic threshold voltage metal-oxide-semiconductor (DTMOS) to suppress the fringing-induced barrier-lowing (FIBL) effect caused by application of high-k gate dielectrics into MOSFET is proposed in this paper. The performance of DTMOS is compared with the conventional MOSFET with high-k gate dielectrics. It is shown that with high-k gate dielectrics introduced into MOSFET, using DTMOS structure can not only retain its good subthreshold and output characteristics resulted from dynamic threshold voltage, but also suppress FIBL effect caused by application of the high-k gate dielectrics and can get better short-channel performance. Devices with different channel doping profile and smaller size are also simulated. Simulated results show that the above mentioned advantages are still remained.