High Density Interconnect Research Articles

3D laser structuring of supermetalphobic microstructures inside elastomer for multilayer high-density interconnect soft electronics

Abstract High-density interconnect (HDI) soft electronics that can integrate multiple individual functions into one miniaturized monolithic system is promising for applications related to smart healthcare, soft robotics, and human-machine interactions. However, despite the recent advances, the development of three-dimensional (3D) soft electronics with both high resolution and high integration is still challenging because of the lack of efficient manufacturing methods to guarantee interlayer alignment of the high-density vias and reliable interlayer electrical conductivity. Here, an advanced 3D laser printing pathway, based on femtosecond laser direct writing (FLDW), is demonstrated for preparing liquid metal (LM)-based any layer HDI soft electronics. FLDW technology, with the characteristics of high spatial resolution and high precision, allows the maskless fabrication of high-resolution embedded LM microchannels and high-density vertical interconnect accesses for 3D integrated circuits. High-aspect-ratio blind/through LM microstructures are formed inside the elastomer due to the supermetalphobicity induced during laser ablation. The LM-based HDI circuit featuring high resolution (∼1.5 μm) and high integration (10-layer electrical interconnection) is achieved for customized soft electronics, including various customized multilayer passive electric components, soft multilayer circuit, and cross-scale multimode sensors. The 3D laser printing method provides a versatile approach for developing chip-level soft electronics.

Warpage in wafer-level packaging: a review of causes, modelling, and mitigation strategies

Wafer-level packaging (WLP) is a pivotal semiconductor packaging technology that enables heterogeneously integrated advanced semiconductor packages with high-density electrical interconnections through its efficient and highly reliable manufacturing processes. Within this domain, fan-out wafer-level packaging has gained prominence due to its potential for high integration capacity, scalability, and performance on a smaller footprint. This review examines FOWLP technology and its associated challenges, primarily warpage. As semiconductor companies strive to develop cutting-edge packages, wafer warpage remains an intrinsic and persistent issue affecting yield and reliability at both the wafer and package levels. Warpage characterization techniques and modeling approaches, including theoretical, numerical, and emerging artificial intelligence and machine learning (AI/ML) methods, have been analyzed. The structural parameters and properties of the constituent materials of the reconstituted wafer and the FOWLP process have been considered to evaluate the effectiveness of these methods in predicting and analyzing warpage. Potential directions and limitations in warpage prediction and mitigation have been outlined for future research for more reliable and high-performance FOWLP solutions.

Thin Glass Interposers with High-Density Interconnects

Glass has excellent electrical and mechanical properties for advanced electronic packaging, and even photonics applications. With a large bulk resistance, low moisture sensitivity, and dimensional stability, glass wafers have properties that allow them to be inserted in many of the processes typically used for silicon, and also allow advantaged performance in some applications, especially those involving high frequency. Thin glass is required to keep latency low and form-factor contained. In this presentation, we will describe the capability to produce void-free, hermetic, copper-filled vias, ranging in aspect ratio from 2:1 to 8:1. We also describe progress in multilayer metallization of thin glass interposers. Five redistribution layers (3 on one side, and 2 on the other) are explored in order to accommodate a relatively high density of interconnects. Daisy-chain structures demonstrate continuity as a function of RDL trace line and space. We report bow measurements on thin glass, exploring the effects of film stress of multiple RDL layers both in a configuration supported by a temporary handle, and free-standing.

Patterning Fine Pitch L/S on Photosensitive PBO Using Laser Direct Imaging for High-Density Interconnect Applications

With the miniaturization and enhanced functionality of devices, integrating various components into sophisticated, high-level packaging has become the new direction, moving beyond the limitations of Moore’s law for transistors. The “More than Moore” approach integrates different functional dies within a single package, relying on dense, high-performance interconnects as its framework. Fan-out wafer-level packaging (FOWLP) has become notable for its ability to connect different chiplets and components, with continued increase in input/output density to improve both electrical and thermal performance, while also being cost-effective and flexible in design. Such packaging necessitates advanced redistribution layers (RDL) for optimized performance. For high-density interconnect applications, various polymers are explored, including polybenzoxazoles (PBO), which is standing out due to its excellent mechanical and thermal properties, along with strong adhesion to various substrates. Meanwhile, for dense and intricate routing, more adaptable lithography methods are needed over traditional hard mask photolithography. Direct laser lithography emerges as a more flexible and economical option. This study delves into the finest line-space resolution achievable through direct laser lithography using a maskless aligner from Heidelberg Instruments, targeting sub-3um L/S ratio with photodefinable PBO. It also evaluates how different processing conditions such as substrate type, photoresist material, thickness, exposure dose, and defocus affect resolution limits.

Cu Pillar Electroplating Using a Synthetic Polyquaterntum Leveler and Its Coupling Effect on SAC305/Cu Solder Joint Voiding.

With the advancement of high-integration and high-density interconnection in chip manufacturing and packaging, Cu bumping technology in wafer- and panel- level packaging is developed to micrometer-sized structures and pitches to accommodate increased I/O numbers on high-end integrated circuits. Driven by this industrial demand, significant efforts have been dedicated to Cu electroplating techniques for improved pillar shape control and solder joint reliability, which substantially depend on additive formulations and electroplating parameters that regulate the growth morphology, crystal structure, and impurity incorporation in the process of electrodeposition. It is necessary to investigate the effect of an additive on Cu pillar electrodeposition, and to explore the Kirkendall voids formed during the reflowing process, which may result from the additive-induced impurity in the electrodeposited Cu pillars. In this work, a self-synthesized polyquaterntum (PQ) was made out with dual suppressor and leveler effects, and was combined with prototypical accelerator bis- (sodium sulfopropyl)-disulfide (SPS) for patterned Cu pillar electroplating. Then, Sn96.5/Ag3.0/Cu0.5 (SAC305) solder paste were screen printed on electroplated Cu pillars and undergo reflow soldering. Kirkendall voids formed at the joint interfaces were observed and quantified by SEM. Finally, XRD, and EBSD were employed to characterize the microstructure under varying conditions. The results indicate that PQ exhibits significant suppressive and levelled properties with the new structure of both leveler and suppressor. However, its effectiveness is dependent on liquid convection. PQ and SPS work synergistically, influencing the polarization effect in various convective environments. Consequently, uneven adsorption occurs on the surface of the Cu pillars, which results in more Kirkendall voids at the corners than at the center along the Cu pillar surface.

Compact multi-port multi-wavelength laser source with Tbps transmission for optical I/O technology.

In this paper, we propose and experimentally demonstrate a novel compact multi-port multi-wavelength laser source (MP-MWL) for the optical I/O technology. The multi-wavelength DFB laser array is used for realizing the simultaneous emission of multiple wavelengths. The reconstruction equivalent chirp technique is used to design and fabricate the π-phase shifted DFB laser array to achieve precise wavelength spacing. The number of wavelengths is enlarged through the monolithically integrated wavelength routing architecture (WRA), and 64 optical carriers are obtained with 8 wavelengths in 8 output ports. The proposed MP-MWL has high mode stability and high uniform wavelength spacing. The side mode suppression ratio (SMSR) of each wavelength is more than 40 dB and the wavelength spacing is 100 GHz under 25 °C working environment. A semiconductor optical amplifier (SOA) is monolithically integrated into each output port to amplify the output power. The output power of each port exceeds 15 mW when the current injected into the SOA is 150 mA. Besides, the relative intensity noise (RIN) of all wavelengths is below -130 dB/Hz, and clear 25 Gb/s NRZ eye grams are obtained for the 64 optical carriers with the external lithium-niobate Mach-Zehnder modulator, with a total transmission rate of 1.6 Tbps. The superior performance of the proposed MP-MWL enables it to be a promising approach for the Tbps optical I/O links and high-density chip interconnection system.

Matrix analysis of high-density arrayed waveguides: Crosstalk suppression by bending

For many photonic devices, crosstalk between densely packed waveguides poses a major problem leading to unreliable or inefficient operation of the device. In this work, a general method for modeling the crosstalk, not only in straight waveguide arrays but also in curved ones, is introduced. The method is based on a matrix analysis of electromagnetic field coupling between closely spaced waveguides. As an example, we show how bending of waveguides in an array reduces the crosstalk. The approach can help overcome the crosstalk problem in a variety of photonic integrated devices, including phased waveguide arrays, arrayed waveguide gratings, optical multiplexers, and high-density interconnects between optical and electronic components. Published by the American Physical Society 2024

Effect of Ni Addtion on Electroless Cu for High Density Interconnect PCB Substrate

Introduction Nowadays, high-density interconnect (HDI) printed circuit board (PCB) substrates have been widely applied to high-end electronics to meet the increasing input and output (I/O) density and small footprint area. Micro-via, a tiny structure buried among build-up layers that provide electrical interconnection is a key component in the HDI substrate. However, the preparation of micro-via is facing new challenges. It is not only required that the size of the micro-via scales down to meet the increased interconnect density, but also that the micro-via should withstand severe operating conditions in different scenarios. Therefore, it is of great importance to improve the quality of micro-vias during processing and manufacturing. The micro-via structure is a sandwich structure that is processed by electroless Cu plating and Cu electrolyte plating sequentially, and thus the quality of the electroless Cu layer can significantly affect the reliability of micro-via. In this work, we mainly focused on the electroless Cu plating process and investigated the effect of the electroless Cu deposition speed on the quality of the micro-via structure. SIM and HR-TEM characterizations were employed to investigate the micro-structure inside the electroless Cu layer. Materials and Method In this study, we used the common alkaline ion catalyst method to prepare the electroless Cu layer. The electroless Cu plating and electrolyte Cu plating was conducted on a PCB Resin Coated Copper (RCC) substrate that was cleaned by soft etching in an acid condition. The surface is then pre-dipped in an anionic solution, and palladium ions were adsorbed using an alkaline ion catalyst. The electroless Cu processes adopted in a reaction bath that consists of Cu resource (CuSO4·5H2O), complexing agent (KNaC4H4O6·4H2O) and reductant (HCHO). The whole reaction was conducted in the alkaline condition with a PH of 12.5, and the thickness of the electroless Cu deposition was controlled at around 0.20 µm. NiSO4 is selected as the Ni precursor to alter the Ni concentration in the reation bath. The contents of Ni addition were selected as 50 %, 100 %, 200 % and 300% of a conventional process at a bath temperature of 27 ºC. The thickness of the plated Cu layer was measured by a gravimetric method. Results and discussion TEM observation was used to identify the structure at the interface. Fig. 1 shows the TEM observation of the sample with 50 % and 200 % Ni concentrate. There are some nanovoids found at the interface between the Cu substrate and electroless Cu, which is arguably due to hydrogen generated during electroless Cu plating. The sample with a higher reaction speed has more nanovoids. It can be due to that the higher reaction speed can generate more hydrogen bubbles in the bath that can attach to the electroless Cu layer, leading to nanovoids as shown in Fig. 1. The samples prepared at different bath temperatures are under investigation to illustrate that the reaction speed can significantly affect the Cu electroless layer quality. Conclusions In this work, we investigated the Ni effect in electroless Cu on the RCC substrate. It is found that the higher Ni incorporation can lead to massive nanovoids generation and fine Cu grains in the electroless layer, which is a potential risk for the reliability of the HDI substrate. By reducing the Ni incorporation content, the number of nanovoids can be effectively reduced. Figure 1

Microstructure Modification and Enhancement in Mechanical Properties Cu/Sn-Ag/Cu Microbump Joints with 5-Micron Bonding Height Via Alloying of Zn and Ni in Cu Ubm

With the rise of artificial intelligence (AI) and the 5G era, advanced microelectronic packaging is gaining attention, shifting towards high-density interconnection and downsizing packaging structures. In response to increasing demands for high power density, low energy consumption, and low latency, 3-dimensional chip stacking technology (3D-IC) has emerged. In 3D-IC structures, Pb-free microbump solder joints, notably with diameters potentially below 10μm, are widely used, exhibiting sizes 10 times smaller than traditional flip chip joints. However, this miniaturization poses challenges, leading to interfacial Intermetallic Compound (IMC) overgrowth and high internal stress due to volume shrinkage and natural brittleness. To address this, Cu-Zn-based substrates are employed, forming a Zinc-rich layer that efficiently reduces IMC thickness. The transition of hexagonal η-Cu6Sn5 to monoclinic η'-Cu6Sn5 and the formation of porous Cu3Sn under certain conditions impact mechanical reliability. The addition of Ni and Zn in solder joints is reported to enhance phase stabilization and mechanical properties. Considering the influence of solder alloy composition on melting points, adding Zn and Ni in substrates is suggested to ensure a stable source of dopants and stabilize molten behavior. Co-doping Zn and Ni in substrates aids in Cu-Sn IMC suppression. Previous work on double-sided Cu-26Zn-18Ni substrates soldering with Sn-3.5Ag solder optimized IMC thickness, inhibiting the brittle Cu3Sn phase and Kirkendall voids, while inducing the tough γ-Cu5Zn8 phase. This phase exhibits favorable toughness and shear modulus, enhancing mechanical strength.This study investigates the microstructure evolution, elemental distribution, and mechanical reinforcement of Cu-26Zn-18Ni/Sn-3.5Ag/Cu-26Zn-18Ni microbumps with a bond height below 10μm. A field emission electron probe micro-analyzer (FE-EPMA) was utilized to examine microstructures and elemental distribution. Additionally, transmission electron microscopy with energy dispersive spectroscopy (TEM/EDS) was employed for detailed voiding formation and phase identification. Electron backscatter diffraction (EBSD) confirmed the presence of highly randomly oriented (Cu,Ni)6(Sn,Zn)5 with a submicron grain size. Fracture modes of the microbumps were characterized through shear tests and correlated with microstructures. In comparison to Cu/Sn-3.5Ag/Cu microbumps, the alternative Cu-Zn-Ni substrates significantly improved shear strength (19.6% to 97.8%) and failure toughness (10.6% to 132.1%) under different reflow times. The microstructure of Cu-26Zn-18Ni/Sn-3.5Ag/Cu-26Zn-18Ni microbumps, featuring solid solution strengthening and refined (Cu,Ni)6(Sn,Zn)5 along with tough bulk (Cu,Ag)5(Sn,Zn)8, demonstrated remarkable toughness.These findings offer valuable insights into the design of microbumps with a bonding height in the sub-10-micron scale. Keywords: Microbump, Shear strength, Microstruture, Intermetallic compounds Figure 1

A Review of Mechanism and Technology of Hybrid Bonding

Abstract With the development of semiconductor technology, traditional flip-chip bonding has been difficult to meet the high-density, high-reliability requirements of advanced packaging technology. As an advanced three-dimensional stacked packaging technology, Cu-SiO2 hybrid bonding technology can achieve high-density electrical interconnection without bumps, which expands the transmission performance and interconnection density of chips greatly. However, the investigation on Cu-SiO2 bonding is far from mature, and many researchers are studying Cu-SiO2 bonding passionately. There are many technologies that use different bonding mechanisms to achieve Cu-SiO2 bonding, which will affect the bonding strength directly. We review the mechanism and research progress of Cu-Cu bonding, SiO2-SiO2 bonding. What is more, we summarize the comparison of bonding conditions and bonding strength of various methods furtherly. According to the bonding mechanism, we propose some economical solutions for low-temperature Cu-SiO2 hybrid bonding, with the aim of providing certain references for the further development of advanced semiconductor packaging.

Photonic-crystal-based hybrid wavelength-mode division multiplexer for SOI platforms

This paper presents a 12-channel hybrid wavelength-mode division multiplexer (WDM-MDM) based on 2D photonic crystals. The proposed device consists of microring resonators (MRRs) and asymmetric directional couplers (ADCs) to perform three-channel wavelength division multiplexing and four-channel mode division multiplexing operations, respectively. Each MRR can work bi-directionally, providing the same wavelength channels separately in two drop ports. The bus waveguides in the cascaded ADCs are optimized to convert the fundamental modes to the corresponding higher-order modes and are connected through taper regions for the smooth transition of modes. The designed device is simulated using the finite-difference time-domain solver, achieving a maximum channel spacing and insertion loss of 5.05 nm and 0.97 dB, respectively. The device size of the proposed WDM-MDM is 74.98µm×32.82µm. The fabrication tolerance study is performed for uniform over-etch and under-etch conditions. The temperature tolerance study on the resonant wavelength is performed, and the temperature coefficient shift of <0.0254nm/K is achieved. The proposed device can potentially increase the channel capacity for on-chip high-density optical interconnects.

Microstructure modification and mechanical reinforcement in sub-10 μm scale Cu/Sn–Ag/Cu microbump joints via Co-addition of Zn and Ni in Cu substrates

Microstructure modification and mechanical reinforcement in sub-10 μm scale Cu/Sn–Ag/Cu microbump joints via Co-addition of Zn and Ni in Cu substrates

Optimization of novel two-step curing method for die stack epoxy bonding to reduce voids in Ball Grid Array packages for high-density interconnect applications

Optimization of novel two-step curing method for die stack epoxy bonding to reduce voids in Ball Grid Array packages for high-density interconnect applications

Ultrahigh Aspect Ratio Through Glass Vias Perforation Utilizing Selective Laser‐Induced Etching with Nanochannels

At present, perforation of high aspect ratio through glass vias (TGVs) is one of the primary factors limiting the development of glass interposers. Herein, it is based on a large number of experiments, combined with mechanistic analysis, to realize the perforation of ultrahigh/high aspect ratio fused silica TGVs using selective laser‐induced etching. First, the effect of the number of pulses as well as other laser parameters on the etching selectivity is systematically investigated. It is found that the formation of nanochannels in fused silica is crucial in determining the high selectivity. Subsequently, a model based on diffusion theory is proposed to mathematically explain the reasons for the high selectivity generation. Finally, the perforations of TGVs with diameters of 5.4–26.4 μm, aspect ratios of 11.7–61.3, and vertical sidewalls are achieved, at a laser treatment speed of ≈10 000 TGVs per minute. This research can serve as an essential reference for the manufacturing of TGVs with high aspect ratios and glass interposers with high interconnection density.

Reliability and thermal fatigue life prediction of solder joints using nanoindentation

Reliability and thermal fatigue life prediction of solder joints using nanoindentation

Recent Progress of TGV Technology for High Performance Semiconductor Packaging

In recent semiconductor packaging, the adoption of through silicon via (TSV) technology has become crucial for the integration of 2.5 and 3D Si chips, and interposers. The TSV offers significant advantages including high interconnect density, shortened signal pathways, and improved electrical performance. However, challenges such as electrical loss, substrate warpage, and high manufacturing costs are associated with TSV implementation. In contrast, glass-based through-glass vias (TGVs) exhibit promising characteristics such as excellent insulation properties, cost-effectiveness, and variable coefficient of thermal expansion (CTE) values that mitigate warpage in stacked devices. Moreover, they facilitate miniaturization and support high-frequency applications. This paper provides an overview of recent advancements in glass substrate, TGV drilling techniques, functional layer depositions, and Cu-filling processes in semiconductor packaging evolution.

Die Crack Prevention and Detection in Advanced Packaging

Semiconductor manufacturers are continuously driving efforts to put more computing power and speed into less volume. At the same time, consumers are demanding devices with more functionality that integrate a variety of interconnected circuit types. The result has been an increasing reliance on advanced packaging technologies that use fab-like processes to integrate multiple chips and to provide the increased I/O capability required. The demand for higher performance electronics in smaller packages has led to the development of wafer level packaging (WLP), panel level packaging (PLP) and fan-out level packaging. The need for low cost, smaller packages with high density interconnects for cell phones and wearable devices has been leading the development of advanced packaging. All of these advanced packaging techniques involve stacking multiple chips in vertical directions. In DRAM memory packaging, there are as many as eight dies integrated vertically and the manufacturers are trying to keep the thickness of the die as minimal as possible to keep an overall thin package profile. Backside thinning of fully processed wafers has become a widely used technique in the industry. Typical final wafer thickness in the early 1990s was around 450µm but current wafers are usually thinner than 50µm. As the final wafer thickness is getting thinner, they are becoming more fragile and susceptible to cracks and chips. Chipping and cracks can cause near-term yield and long-term reliability problems. If a chip or crack is discovered during the final processes of advanced packaging, the overall final yield will be lower. If it is not discovered, the end device may not be reliable in the real world and fail for the consumer, a more costly consequence. As wafers became thinner, the industry started seeing sidewall cracks, inner cracks and micro cracks starting from the kerf or street area initiated from wafer sawing. These types of cracks can cause air bubbles around the cracks during the molding process in fan-out packaging and eventually lead to mold cracking which can lead to lower yields. It would be very beneficial if these types of cracks are detected early and the affected die removed. However, these types of cracks are happening underneath the die surface and are difficult to see with traditional bright field and dark field illuminations because they are underneath the top surface. Consumer tolerance for device failure is at an all-time low, as they demand more functionality and more convenience from their electronic devices. Wafer level packaging (WLP), panel level packaging (PLP) and fan-out level packaging advanced packaging techniques all involve extensive use of bumps and die thinning to establish electrical connections in vertical directions. Packaging these vertically integrated die requires the need to provide interlayer connections that are as small and reliable as the multilayer interconnect technologies used within the chip. This need for vertical connections has created a whole new class of technologies; advanced packaging; with a whole new lexicon of terms and acronyms: through-silicon vias (TSVs), redistribution layers (RDLs), bumps, pillars, nails, under bump metallization (UBM), wafer-level packaging (WLP), fan-in, fan-out, and many more. All of these technologies serve the purpose of providing reliable, electrically isolated, vertical connections, and most, at some point, involve the creation of a conductive; ump; protruding through an insulating layer to carry the signal to the next layer above or below. As more chips are integrated vertically, overall package thickness increased as well and the common ways to reduce the overall package thickness are by thinning chips or die and reducing bump sizes. As die or chips are getting thinner, they become more fragile and susceptible to cracks or chippings. Cracks or chips can reduce the final package yields or cause long term reliability issues in the consumer devices. This paper describes inspection challenges for cracks underneath the die surface and possible solutions to overcome the challenges.

A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM.

A multi-layer stacked Dynamic Random Access Memory (DRAM) platform is introduced to address the memory wall issue. This platform features high-density vertical interconnects established between DRAM units for high-capacity memory and logic units for computation, utilizing Wafer-on-Wafer (WoW) hybrid bonding and mini Through-Silicon Via (TSV) technologies. This 3DIC architecture includes commercial DRAM, logic, and 3DIC manufacturing processes. Their design documents typically come from different foundries, presenting challenges for signal integrity design and analysis. This paper establishes a lumped circuit based on 3DIC physical structure and calculates all values of the lumped elements in the circuit model with the transmission line model. A Cross-Process Signal Integrity Analysis (CPSIA) method is introduced, which integrates three different manufacturing processes by modeling vertical stacking cells and connecting DRAM and logic netlists in one simulation environment. In combination with the dedicated buffer driving method, the CPSIA method is used to analyze 3DIC impacts. Simulation results show that the timing uncertainty introduced by 3DIC crosstalk ranges from 31 ps to 62 ps. This analysis result explains the stable slight variation in the maximum frequency observed in vertically stacked memory arrays from different DRAM layers in the physical testing results, demonstrating the effectiveness of this CPSIA method.

3-((2-ethoxyethanethioyl)thio)propane-1-sodium sulfonate as a new accelerator for copper electroplating: Electrochemical and theoretical calculation studies

3-((2-ethoxyethanethioyl)thio)propane-1-sodium sulfonate as a new accelerator for copper electroplating: Electrochemical and theoretical calculation studies

A Novel Photosensitive Permanent Bonding Material for Polymer/Metal Hybrid Bonding

Wafer-level hybrid bonding techniques, which provide simultaneous bonding between metal-metal and between dielectric-dielectric layers, has attracted more attention in recent years for fabricating 3D integrated circuits with high bandwidth and high interconnect density. However, there are some issues for conventional hybrid bonding using silicon oxide as the dielectric, such as the high stress and low tolerance to height difference of bonding interface, which limits its applications for 3D heterogeneous integration. In this paper, a novel negative-tone photosensitive polymeric bonding material is proposed to be used as a dielectric to enable polymer/metal hybrid bonding. Compared to silicon oxide, the polymeric material with low Young’s modules is able to absorb thermally induced stress created during bonding process and results in lower bow for the bonded substrates. The key features for the photosensitive permanent bonding material include 1) low dielectric constant and dissipation factor; 2) superior thermal stability (>350°C); 3) excellent fine-pitch capability (4 micron); and 4) low processing and curing temperatures (<200°C). The photosensitive permanent bonding material has also been demonstrated to be able to be patterned and bonded to another Si or glass substrate with good adhesion and no obvious defects. The details of the material characterization, process optimization, reliability, and preliminary polymer/metal hybrid bonding results will be presented in the paper.