High Gate Voltage Research Articles

Physical and electrical properties of plasma nitrided germanium oxynitride

The physical and electrical properties of plasma nitrided germanium oxynitride (GeON) and silicon oxynitride (SiON) layers are studied. In this study, two kinds of plasma nitridation process were utilized to form oxynitride layers. High pressure remote inductive coupled plasma and low pressure radial line slot antenna (RLSA) plasma provide radical dominant and ion dominant plasma nitridation processes, respectively. X-ray photoelectron spectroscopy results show different properties of GeON layers based on each plasma nitridation process. The remote (radical) plasma nitridation forms water soluble nitrogen-germanium bonding, and RLSA (ion) plasma nitridation forms water resistant nitrogen-germanium bonding. Although hydrogen containing plasmas or ion dominant plasma process can incorporate high amount of nitrogen into oxynitride layers, such process is accompanied by water insoluble suboxide formation and charging damage. Using p-type metal oxide semiconductor (MOS) capacitors, basic electrical properties of GeON and SiON films were also studied. Approximately four order magnitude higher gate leakage current was observed on GeON MOS capacitor, which results in capacitance reduction and a large dissipation factor at high gate voltage.

An optimization technique for parameter extraction of ultra-deep submicron LDD MOSFET’s

An optimization technique to determine the threshold voltages Vth is proposed for meaningful parameter extractions of ultra-deep submicron LDD MOSFETs. The novel technique, coupled with some traditional Vth determination techniques, are implemented in several existing extraction methods to extract the parasitic series resistance Rds, the effective channel length Leff , and the effective mobility μeff of ultra-thin gate oxide LDD MOSFETs on 90nm CMOS technology. A comparison among these extractions demonstrates that the technique of Vth optimization maintains the accuracy of extractions, avoids the intentional choice of the gate voltage range, and eliminates the impact of close interdependence among these parameters on the meaningful extraction, especially at high gate voltage range. Furthermore, the novel technique can reduce the extraction variance of different extraction methods, hence, suitable for application in device compact model.

Field-induced mobility degradation in pentacene thin-film transistors

Pentacene-based organic thin-field transistors (OTFTs) with bottom-gate, top-contact architecture were fabricated on alumina substrates. The devices were divided into two sets, depending on whether pentacene was deposited on bare alumina or on alumina modified with a fatty acid self-assembled monolayer (SAM). Previous analysis have shown that the modification of alumina with SAMs result in a substantial decrease of the size of the grains in hte polycrystalline films. Careful parameters extraction, including an original determination of the threshold voltage, and contact resistance extraction through the transfer line method (TLM), allowed us to estimate the gate-voltage dependent mobility in both series. The mobility is found to first increase at low bias, and then decrease at higher gate voltage (mobility degradation). The latter behavior is explained through an estimation of the distribution of charges across the accumulation layer, in which the pentacene film is modeled as a stack of dielectric layers, the distribution being calculated using basic equations of electrostatics and thermodynamics. A good agreement was found when the mobility in the layer next to the insulator was assumed to be negligible as compared to that in the bulk of the film. The initial rise of the mobility is interpreted in terms of multiple trap and release (MTR) with a distribution of traps located in the grain boundaries. Interestingly, the mobility corrected for both contact resistance and mobility degradation is found around 3 cm2/V s for pentacene deposited on bare alumina, and 5 cm2/V s when pentacene is deposited on SAM modified alumina. We conclude that the smaller grains grown on modified alumina are more regular, and hence less defective, than the larger grains deposited on bare alumina.

Characterization of functionalized pentacene field-effect transistors and its logic gate application

Functionalized pentacene, 6,13-bis(tri-isopropylsilylethynyl)pentacene (TIPS-pentacene), field-effect transistors (FETs) were made by both thermal evaporation and solution deposition methods, and the mobility was measured as a function of temperature and intensity of incident illumination. The field-effect mobility (μFET) has a gate-voltage dependent activation energy. A nonmonotonic temperature dependence was observed at high gate voltage (VG<−30V) with an activation energy of Ea∼60–170meV, depending on the fabrication procedure. The gate-voltage dependent mobility and nonmonotonic temperature dependence indicate that shallow traps play important role in the transport of TIPS-pentacene films. The current in the saturation regime as well as the mobility increase upon light illumination in proportion to the light intensity, mainly due to the photoconductive response. Transistors with submicron channel length showed unsaturating current-voltage characteristics due to the short channel effect. Realization of simple circuits such as NOT (inverter), NOR, and NAND logic gates are demonstrated for thin film TIPS-pentacene transistors.

Numerical and experimental characterization of 4H-silicon carbide lateral metal-oxide-semiconductor field-effect transistor

Combined simulation and experimental analyses are performed to characterize the 4H-silicon carbide (SiC) lateral metal-oxide-semiconductor field-effect transistor (MOSFET). Using a quasi-two-dimensional depth dependent Coulomb mobility model for scattering due to interface and oxide charge, along with existing models for other scattering mechanisms, and an in-house drift diffusion device simulator tailored for SiC MOSFETs, we have extracted values for interface trap density of states for 4H-SiC MOSFETs. Characterization shows that the interface trapped charge in 4H-SiC MOSFETs is responsible for mobility degradation and reduction in mobile inversion charge, and therefore reduced current. Its effect on mobility degradation decreases at higher gate voltages due to increased screening. Our results show that at high gate voltages, surface roughness plays the major role in surface mobility degradation in 4H-SiC MOSFETs. Results indicate that due to high Coulomb scattering near the interface, current density is maximum a few nanometers away from the surface. The model indicates overall mobility values of approximately 20cm2∕Vs at the interface, and increasing to approximately 250cm2∕Vs near the bottom of the inversion layer. Simulations predict that tenfold reduction in interface and fixed oxide charge density would give rise to very favorable device characteristics.

Examination of degradation mechanism due to negative bias temperature stress from a perspective of hole energy for accurate lifetime prediction

An evaluation method using the modified hole injection method is proposed to evaluate Negative Bias Temperature Instability (NBTI) in this paper. The physical backgrounds of the evaluation method are strictly discussed. The proposed method accelerates the degradation such as the threshold voltage ( V th) shift by the amount of the hole injection without the high gate voltage stress. Our experimental and theoretical frameworks clarify that two degradation mechanisms, one follows the reaction–diffusion (R–D) model and another follows the hole trap/de-trap (HTD) model, coexist in NBTI. In the inversion layer, holes distributed in the quantized upper energy levels especially induce the degradation that follows the R–D model, and holes distributed in the ground energy level induce the degradation that follows the HTD model. Finally, the accurate NBTI lifetime prediction is demonstrated using the proposed acceleration method.

A low gate bias model extraction technique for AlGaN/GaN HEMTs

The small-signal equivalent circuit of AlGaN/GaN high electron-mobility transistors is discussed. A new modeling procedure is introduced in this paper that does not bias the device at a untenable high gate voltage in order to extract the parasitic inductance and resistance. Simulated results show good agreement with measurements up to 40 GHz.

Electronic properties of Ge nanocrystals for non volatile memory applications

Charge and discharge phenomena of Germanium nanocrystals fabricated by low pressure chemical vapor deposition are investigated by means of Capacitance–Voltage and capacitance decay measurements. The study shows fast programming and erasing times as compared with conventional devices. It is shown that the charge saturation depends on the gate voltage stress in the low electric field regime. For high gate voltages, a saturation of the stored charge is obtained, indicating that the density of trapped carriers in Ge nanocrystals is limited and depends only on the dots size. Capacitance decay measurements exhibits a very long retention time for holes as compared with silicon nanocrystal memories. This is mainly due to the barrier height for holes at the nc-Ge/ 2 interface. A model for simulation of the retention kinetics has been developed and allows to extract the band alignment of the nc-Ge/SiO2/Si system. The simulation results are then used to determine the band gap energy of Ge nanocrystals. Finally, it is shown that Ge nanocrystals are very good candidates for P-type Metal Oxide Semiconductor nonvolatile memories.

Hole Confinement and 1/ f Noise Characteristics of SiGe Double-Quantum-Well p-Type Metal–Oxide–Semiconductor Field-Effect Transistors

A working p-type SiGe double-quantum-well metal–oxide–semiconductor field effect transistor (DQW-pMOSFETs) has been fabricated and characterized. The upper quantum well with 15%-Ge acts as an induced-carrier buffer to slow holes into the Si surface channel and increases the number of high-mobility holes in the 30%-Ge well at the bottom under high gate voltage by improving carrier confinement. DQW devices with a thinner Si-spacer layer between the two SiGe quantum wells exhibit an improved effective hole mobility and wider gate voltage swings but also reduced 1/ f noise levels than Si-controlled pMOSFETs. The DQW has an enhanced carrier confinement compared to a single quantum-well (SQW) device; however, the degradation of mobility and transconductance observed in a sample DQW indicates that this poor transport mechanism may result from an additional hole scattering effect at the Si/SiGe interface.

On the saturation mechanism in the Ge nanocrystals-based non-volatile memory

The hole charging mechanism in Germanium nanocrystals (nc-Ge) embedded in SiO2 fabricated by low pressure chemical vapour deposition is investigated by means of capacitance–voltage (C–V) analysis. The charging kinetics shows a logarithmic behaviour and a saturation phenomenon for various gate voltage stresses. For low gate bias stresses, the saturation of the carrier number in the nc-Ge seems to depend on the electric field in the oxide. On the other hand, we have demonstrated that for high gate voltage stresses, the number of holes per dot at saturation becomes constant and depends only on the diameter of the nc-Ge. Finally we propose a model to explain the saturation mechanism. This model is then used to extract the nanocrystals size.

Hopping Transport and Voltage Induced Metal-Insulator Transition in Polythiophene Field Effect Transistors

ABSTRACTWe have studied the carrier transport in regio-regular polythiophene field effect transistors (FETs) by four-probe measurements of the steady-state channel conductance from room temperature to 4.2 K. At high gate voltage (constant total carrier density, n = 5×1012 cm−2) and at low temperatures, we demonstrate that the gate voltage and source-drain voltage combine to induce the insulator-to-metal transition. In the insulating regime, the carrier transport is well described by phonon assisted hopping in a disordered Fermi Glass (with Coulomb interactions between the hopping charge carrier and the charge left behind). At the highest gate voltages and at sufficiently high source-drain voltages, the data imply a zero-temperature transition from disordered insulator to metal.

High-frequency performance projections for ballistic carbon-nanotube transistors

A quasi-static approach is combined with a theory of ballistic nanotransistors to assess the high-frequency performance potential of carbon-nanotube field-effect transistors. A simple equivalent circuit, which applies in the ballistic limit of operation, is developed for the intrinsic device, and then employed to determine the behavior of the unity-current-gain frequency (f/sub T/) with gate voltage. The circuit is shown to reduce to the expected forms in the so-called MOS and bipolar limits. The f/sub T/ is shown to approach a maximum value of v/sub F//2/spl pi/L/spl ap/130 GHz/L (/spl mu/m) at high gate voltage, where v/sub F/ is the nanotube's Fermi velocity and L is the channel length, and to fall at low gate voltage due to the presence of source and drain electrostatic capacitances. The impact of the gate electrostatic capacitance on the f/sub T/ is also discussed. Numerical simulations on a MOSFET-like or bulk-switched carbon-nanotube transistor are shown to support the conclusions.

Gate oxide reliability in an integrated metal-oxide-semiconductor field-effect transistor-microelectromechanical system technology

We have demonstrated a simple technique for building n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and complex micromechanical systems simultaneously instead of serially, allowing a more straightforward integration of complete systems. The fabrication sequence uses few additional process steps and only one additional masking layer compared with a microelectromechanical system (MEMS)-only technology, but exposes the MOSFET gate oxide to the extreme temperatures of MEMS processing. We find that the high-temperature MEMS anneals can greatly change the current-voltage characteristics of the SiO2 gate oxide film. Defects are introduced by the high-temperature processing which result in considerable positive-charge trapping at short times that leads to increased currents using high bias fields and short bias times. At longer times, the current across the oxide decays as 1/time suggesting electron traps that are uniformly distributed in the bulk of the oxide. A traditional reliability evaluation of the thick oxides using time-dependent dielectric breakdown is greatly hampered by excessive impact ionization that occurs at high gate voltages. This makes a rigorous evaluation of gate oxide lifetime at use fields difficult. We do note that while the current below breakdown is altered by the positive-charge trapping, the voltages at breakdown seen in ramps are not severely impacted by the high-temperature annealing. Breakdown voltages of films annealed at the highest of the temperatures studied here are about the same as those of unannealed films. The breakdown fields of these stressed oxides are 10–11MV∕cm, suggesting that reliable SUMMiT™ field-effect transistor process gate oxides can be fabricated as long as the use voltage is well below the onset for impact ionization.

Substrate and process dependence of gate oxide reliability of 0.18μm dual gate CMOS process

V-ramp method was used to evaluate gate oxide reliability of 0.18μm dual gate CMOS process. Charge of breakdown (Qbd) and voltage of breakdown (Vbd) of gate oxide with n-type substrate and p-type substrate were extracted. It was found that for low voltage (thin oxide) gate oxide device the Qbd of gate oxide of n-type substrate and p-type substrate are almost the same, but for high voltage (thick oxide) gate oxide device the Qbd of n-type substrate and p-type substrate have a big difference. At the same time, Qbd of gate oxide with p-substrate is bigger than that of gate oxide with n-substrate. The difference of Qbd of thin gate oxide and thick gate oxide can be attributed to lithographic damage to the interface of poly-silicon gate and thick gate oxide. There is a big difference between the Weibull slopes of charge of breakdown of thin oxide and thick oxide. For the voltage of breakdown, Similar difference between n-substrate and p-substrate gate oxide was also observed. However, there is no big difference between the Weibull slopes of voltage of breakdown of thin oxide and thick oxide.

Performance Analysis of the Segment npn Anode LIGBT

The performance of a high-voltage lateral insulated gate bipolar transistor (LIGBTs) with segmented n+p/n anode fabricated in junction isolation technology is experimentally investigated at both room and elevated temperatures. Detailed two dimensional numerical modeling of a vertical representation of the structure shows that significant electron current passes through the n/sup +/p/n segment of the anode region during the on-state and when devices are subjected to clamped inductive switching. It is shown that the magnitude of electron current can be controlled by modifying the p-base charge which enables enhancement of the turn-off loss/forward voltage drop tradeoff in comparison to conventional LIGBTs.

GATE LENGTH SCALING AND MICROWAVE PERFORMANCE OF DOUBLE GATE NANOTRANSISTORS

A detailed analysis of static and dynamic characteristics of deep submicron double and single gate SOI MOSFETs is presented, based on 2D numerical simulations for high frequency analog applications. Results show that although DG MOSFET offers excellent performance with respect to short channel immunity and higher transconductance, it offers nearly two times the value of gate-to-source capacitance as compared to SG devices, thus limiting the cut-off frequency at higher gate voltages. At ultra short channel lengths and low gate overdrive voltages, DG devices show a significant improvement in cut-off frequency compared to SG devices, thus presenting DG nanotransistors as potential candidates for analog microwave applications.

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.

Modified PEDOT-PSS Conducting Polymer as S/D Electrodes for Device Performance Enhancement of P3HT TFTs

Poly(3,4-ethylenedioxythiophene)-Polystyrene Sulfonate (PEDOT-PSS) is the most widely used conducting polymer as electrode material in organic (polymer) devices. However, commercially available PEDOT-PSS in our experiment has a relatively low conductivity that reduces the device performance when it is used for electrode material. The purchased PEDOT-PSS has been mixed with polar solvent dimethyl sulfoxide, which increases its conductivity from 0.07 to 30 S/cm. The enhanced conductivity has long-term stability at room temperature and short-term stability at high temperature (100/spl deg/C) in air ambient. The modified PEDOT-PSS has been inkjet printed and used as source/drain (S/D) electrodes for poly(3-hexylthiophene) (P3HT) thin-film transistors (TFTs). Unmodified PEDOT-PSS and gold have also been used as S/D electrodes for comparison. The TFTs with modified PEDOT-PSS electrodes show significantly improved performance over the devices with unmodified PEDOT-PSS electrodes and are similar to the devices with gold electrodes. The difference in device performance mainly results from parasitic series resistance. In the devices with unmodified PEDOTT-PSS, high electrode series resistance has several effects on devices, e.g., restricted current growth at high negative gate voltage, reduced on/off current ratio and current output capability.

Suppression of the unconventional metallic behavior by gate voltage in MWNT device

We observed an ambipolar behavior in multiwalled carbon nanotubes (MWNT) in a back-gate configuration, which allowed us to perform systematic inspection of the low-temperature transport properties against gate voltage. Power-law behaviors in temperature and bias-dependent conductance, disappeared when a high gate voltage was applied, and conductance became temperature- and bias independent. This indicates a gate-induced transformation from the unconventional to the normal metallic states in MWNT.

Analysis of high-power IGBT short circuit failures

The next linear collider (NLC) accelerator proposal at Stanford Linear Accelerator Center (SLAC, Menlo Park, CA), requires a highly efficient and reliable, low cost, pulsed-power modulator to drive the klystrons. A solid-state induction modulator has been developed at SLAC to power the klystrons; this modulator uses commercial high voltage and high current insulated gate bipolar transistor (IGBT) modules. Testing of these IGBT modules under pulsed conditions was very successful; however, the IGBTs failed when tests were performed into a low inductance short circuit. The internal electrical connections of a commercial IGBT module have been analyzed to extract self- and mutual partial inductances for the main current paths as well as for the gate structure. The IGBT module, together with the partial inductances, has been modeled using PSpice. Predictions for electrical paths that carry the highest current correlate with the sites of failed die under short circuit tests. A similar analysis has been carried out for a SLAC proposal for an IGBT module layout. This paper discusses the mathematical model of the IGBT module geometry and presents simulation results.