High Gain Low Noise Amplifier Research Articles

A 2–20-GHz Ultrawideband High-Gain Low-Noise Amplifier With Enhanced Stability

A 2–20-GHz Ultrawideband High-Gain Low-Noise Amplifier With Enhanced Stability

A 26-28 GHz, Two-Stage, Low-Noise Amplifier for Fifth-Generation Radio Frequency and Millimeter-Wave Applications.

This paper presents a high-gain low-noise amplifier (LNA) operating at the 5G mm-wave band. The full design combines two conventional cascode stages: common base (CB) and common emitter (CS). The design technique reduces the miller effect and uses low-voltage supply and low-current-density transistors to simultaneously achieve high gain and low noise figures (NFs). The two-stage LNA topology is analyzed and designed using 0.25 µm SiGe BiCMOS process technology from NXP semiconductors. The measured circuit shows a small signal gain at 26 GHz of 26 dB with a gain error below 1 dB on the entire frequency band (26-28 GHz). The measured average NF is 3.84 dB, demonstrated over the full frequency band under 15 mA current consumption per stage, supplied with a voltage of 3.3 V.

Design a Broad-band High flatness Gain Low Noise Amplifier for radar Applications

Design a Broad-band High flatness Gain Low Noise Amplifier for radar Applications

Design of a Source Degenerated Cascode Stage Low Noise Amplifier for 5G Applications

Low Noise Amplifier (LNA) is the most critical part of a receiver front end in terms of the receiver performance. The performance tradeoff among input matching, noise figure, gain, and linearity are analyzed in detail. The LNA finds its application at Portable GPS Receiver, BLE, Zigbee, NFC, WiFi, Wireless Sensor Network, RFIC operating at 2.4GHz frequency. Millimeter wave communication is an evolving technology for bandwidth demanding 5G wireless application. A high gain and linear narrowband cascode Low Noise Amplifier (LNA) operating at 2.18GHz to 2.47GHz is proposed. To demonstrate design methodology, a narrow-band source degenerated cascode LNA is designed and simulated in a standard 90nm CMOS process to operate in the 2.4 GHZ band. The LNA achieves a voltage gain of 5.38dB, Noise figure of 4.1127dB, and from 3.2 V supply voltage. Proper input and output impedance matching have been performed to achieve the input return loss of -14 dB (S11) and output return loss of -19.72 dB (S22). Simulation study has been done using Cadence spectre.

A 0.4-V High-Gain Low-Noise Amplifier Using a Variable-Frequency Image-Rejection Technology

A 0.4-V high-gain low-noise amplifier (LNA) using a variable-frequency image-rejection technology in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process has been proposed. By using forward body biasing and folded topology, the supply voltage and power consumption can be reduced. For achieving low power consumption and small chip area, a feedback capacitor is used to shrink the size of the inductors of the input impedance matching. Moreover, a gain-enhancement-and-image-rejection (GEIR) circuit including an inductor and a variable capacitor is proposed for achieving GEIR simultaneously. The image-rejection frequency can be altered for avoiding strong image signals by the variable capacitor. The proposed LNA shows the measured results including a 15-dB power gain, a 2.6-dB noise figure, and a &#x2212;13-dBm input third-order intercept point at 2.4 GHz, respectively. And the measured variable image rejection ratio ranges from 14 to 39 dBc around 3&#x2013;3.6 GHz for avoiding strong image signals. The measured <inline-formula> <tex-math notation="LaTeX">$P_{\text {dc}} $ </tex-math></inline-formula> is 0.8 mW.

Design and implementation of a broad-band high gain low noise amplifier for 3G/4G applications

The main aim of the paper is designing and implementing a broadband low-noise-amplifier (LNA) based on compensated matching network techniquein order to get high stable gain, low noise figure, low cost and smaller sizefor 3G/4G communication system applications at 2 GHz with bandwidth 600MHz. The Advanced Design System simulates the proposed circuit (ADS).The implementation was done with a class A bias circuit and a low noise transistor BFU 730F with a lower Noise Figure (NFmin) 0.62 dB. Collectorcurrent is measured to be 5.8mA and base current is 19.1μA with a supply voltage of 2.25V. The new design proposed a (NFmin) of 0.62 dB with a 17.8dB high stable amplifier gain. The microstrip lines (MSL) and compensated matching network techniques were used to improve the LNA’s stability and achieve a good result. The LNA board is implemented and assembled on the FR4 botton layer material. The results are virtually non existence equivalent between the simulated and the measured results.

A W‐band preamplified MMIC power detector for passive imaging applications

AbstractThis article presents a W‐band preamplified power detector (PD) monolithic microwave integrated circuit (MMIC). The chip consists of a pseudomorphic high electron mobility transistor (pHEMT) PD with a six‐stage low noise amplifier (LNA) in a commercial 0.1‐μm GaAs pHEMT technology. In order to reduce the high risk of oscillating in a multistage LNA, a circulator‐based method for LNA interstage stability simulation, along with the concept of loop gain, is introduced and analyzed. The simulated loop gain of each node of the LNA is calculated through the proposed method to ensure the unconditional stability for the six‐stage LNA. By incorporating the high gain LNA over 32 dB in the front‐end of the PD, the measured chip achieves a peak responsivity of 3.4 MV/W and a minimum noise equivalent power (NEP) of 95 fW/Hz1/2 both at 85 GHz. To the best of the authors' knowledge, the proposed PD exhibits the best responsivity and NEP in published W‐band GaAs PD MMICs.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

A 21-to-41-GHz High-Gain Low Noise Amplifier With Triple-Coupled Technique for Multiband Wireless Applications

This brief presents a wideband millimeter-wave (mm-Wave) low noise amplifier (LNA) with a triple-coupled technique for multiband wireless applications. To enlarge the gain and reduce the supply voltage, a modified cascode topology exploiting a triple-coupled transformer is developed. Thanks to the transformer, the transconductance of the common-gate (CG) transistor of the cascode topology is also effectively boosted, and hence the gain is further increased. Furthermore, high-order networks, which are realized by combinations of π- and T/L-type structures or transformers, are employed to implement the input, inter-stage, and output impedance matchings. They significantly broaden the bandwidth of the circuit. The LNA is demonstrated using a commercial 65-nm CMOS process. The measurement results show that the circuit achieves a maximum gain of 28.5 dB and a 3-dB gain bandwidth of 20 GHz with 32-mW dc power consumption ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> ). The measured noise figure (NF) and input 1-dB gain compression point ( IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ) are 2.7~3.2 dB and -24.6~-20.4 dBm, respectively, over the entire operating bandwidth.

A High Gain Low-Noise Amplifier Based on ITO-Stabilized ZnO Thin-Film Transistors

A novel high gain low-noise analog amplifier based on n-type indium tin oxide (ITO)-stabilized ZnO thin-film transistors (TFTs) was studied in this work. Amplifiers with capacitor bootstrap structure are proposed. The effect of unequal numbers of bootstrap structure, various capacitance, and different circuit topology on the gain and noise of circuits were investigated. The input referred noise of five kinds of amplifier circuits, Amp1, Amp2 (C444, C333, C422), and Amp3 were measured to be 101.1, 44, 47.3, 43.5, and $38.3~\mu \text{V}_{rms}$ , respectively, and the gains are 19.5, 28.8, 26.8, 25.7, and 32 dB, respectively. It is found that as the numbers of bootstrap structure increase in a small range, the input referred noise decreases, and the circuit gain increases. The effects of the capacitance on the gain or noise can be negligible. And also, the gain of the circuit with cascode structure is higher than that with common source. Results show that the noise is much lower than that of a-InGaZnO (IGZO) TFTs technology, which is widely used in TFT circuits design. The proposed high gain and low-noise analog amplifier with the ITO-stabilized ZnO TFTs technology has great potential in the biomedical fields like electro cardiogram (ECG) and pulse detection, as well as wearable electronic applications.

Graphical approach to designing high‐gain low‐noise MWPLs

This study introduces an analytical approach to compromise between the figures of merit of a microwave photonic link (MWPL) and accordingly to design its corresponding matching networks using a graphical tool such as the Smith chart. In particular, the concept of constant gain and noise figure circles in the Smith chart is introduced in the field of microwave photonics. An analytical approach is used and expressions for circles of constant gain and noise figure are derived for unconditionally stable MWPLs. Then a procedure for designing high-gain low-noise MWPLs in the Smith chart is presented which involves trade-offs between gain and noise figure. Since the presented systematic approach is similar to the one used in high-gain low-noise amplifier design, using this approach to designing the intrinsic link leads to a consistency in the whole design procedure.

Optimal design of a 5.5-GHz low-power high-gain CMOS LNA using the flower pollination algorithm

The design of a low-power, high-gain, highly linear complementary metal–oxide–semiconductor (CMOS) cascode low-noise amplifier (LNA) with an inductive source degeneration circuit for use at 5.5 GHz frequency is optimized using a flower pollination algorithm (FPA) as an evolutionary technique. The FPA is applied to optimize the noise figure (NF) while validating all the design constraints, e.g., on the gain, power dissipation, linearity, stability, and input and output matching. Optimal sizing of the MOS transistors present in the LNA circuit is achieved by using the FPA. Moreover, the FPA helps to estimate the optimal values of the other elements in the LNA circuit. The FPA-based optimal design parameters are used to implement the CMOS LNA circuit in CADENCE IC 6.1.6 software at the UMC 180-nm technology node with a supply voltage of 1.8 V. The designed LNA achieves an input third-order intercept point (IIP3) of 1.77 dBm, power dissipation of 4.29 mW, NF of 0.686 dB, and gain of 24.42 dB at 5.5 GHz. The FPA-based optimal design for the CMOS cascode LNA yields remarkably improved results compared with those in previous literature in terms of the gain, noise figure, power dissipation, and area.

A 2–20 GHz SiGe HBT single-stage cascode LNA with linearity enhancement

A wideband high-gain low-noise amplifier (LNA) with improved linearity is presented in this paper. To suppress the gain compression of large signal under high gain conditions, the single-stage cascode topology using resistive shunt-shunt feedback and an emmiter degenerate resistor are adopted. Wideband input matching is thus realized in conjunction with the preceding L-type passive network. A passive network inserted between the cascode structure and load enhances the gain bandwidth as well as the impedance matching. The LNA is based on a 0.18μm SiGe HBT BiCMOS process and the post simulation results show that the LNA features 2–20 GHz bandwidth, 16.1–18.1 dB power gain and 2.5–3.7 dB noise figure (NF). It exhibits input 1-dB compression point of −12dBm above 14 GHz and consumes 55 mW power form a 3.3-V supply. The chip size is 0.435 mm2 without pads.

Design and Comparison of Low Power High Gain and Low Noise Figure LNA for ISM Applications

Objectives: This paper represents the design and simulation of LNA (Low Noise Amplifier) for ISM (Industrial, Scientific and Medical) applications operating in the 2.4-2.5 GHz band. Methods/Statistical Analysis: In this paper, a very accurate topology named inductive source degeneration topology has been used to provide low NF (Noise Figure), high S21 (forward gain) and very low Power Consumption (PC). The simulation was made through using Advance Design System (ADS) software. Findings: The proposed work prominence on reduction in Noise Figure with increase in power gain at low power consumption as compared to published previous results at 1.2 V power supply. Improvements: This is done in three steps (three different schematic designs) i.e. start with very basic LNA design to proposed LNA design and presents the comparison of all three designed circuit simulations.

A Wide-Band High-Gain Compact SIS Receiver Utilizing a 300- $\mu$W SiGe IF LNA

Low-power low-noise amplifiers integrated with superconductor–insulator–superconductor (SIS) mixers are required to enable implementation of large-scale focal plane arrays. In this work, a 220-GHz SIS mixer has been integrated with a high-gain broad-band low-power IF amplifier into a compact receiver module. The low noise amplifier (LNA) was specifically designed to match to the SIS output impedance and contributes less than 7 K to the system noise temperature over the 4–8 GHz IF frequency range. A receiver noise temperature of 30–45 K was measured for a local oscillator frequency of 220 GHz over an IF spanning 4–8 GHz. The LNA power dissipation was only 300 $\mu$ W. To the best of the authors’ knowledge, this is the lowest power consumption reported for a high-gain wide-band LNA directly integrated with an SIS mixer.

A High Gain and High Harmonic Rejection LNA Using High Q Series Resonance Technique for SDR Receiver

This paper presents a high gain and high harmonic rejection low-noise amplifier (LNA) for software-defined radio receiver. This LNA exploits the high quality factor (Q) series resonance technique. High Q series resonance can amplify the in-band signal voltage and attenuate the out-band signals. This is achieved by a source impedance transformation. This technique does not consume power and can easily support multiband operation. The chip is fabricated in a <TEX>$0.13-{\mu}m$</TEX> CMOS. It supports four bands (640, 710, 830, and 1,070MHz). The measured forward gain (<TEX>$S_{21}$</TEX>) is between 12.1 and 17.4 dB and the noise figure is between 2.7 and 3.3 dB. The IIP3 measures between -5.7 and -10.8 dBm, and the third harmonic rejection ratios are more than 30 dB. The LNA consumes 9.6 mW from a 1.2-V supply.

Low Noise Figure, High Gain Single LNA Cascaded with Cascoded LNA Amplifiers using Optimized Inductive Drain Feedback for Direct Conversion RF Front-end Receiver at Wireless Application

This study presents a design of low noise figure, high gain LNA at 5.8 GHz with cascaded and cascoded techniques using inductive drain feedback that is applicable for the WiMAX 802.16 standard. The amplifier uses Pseudomorphic High Electron Mobility Transistor FHX76LP super HEMT low noise FET. The Ansoft Designer SV as an Electromagnetic (EM) simulator was used during the design process. The LNA was designed using the inductive drain feedback, inductive generation to the source and the T-network as a matching technique was used at the input and output terminal. The cascaded and cascoded Low Noise Amplifier (LNA) produced a gain (S21) of 43.94 dB and the Noise Figure (NF) of 0.61 dB. The input reflection (S11), output reflection (S22) and return loss (S12) are -10.65, -20.02 and -52.23 dB, respectively. The measured 3 dB bandwidth of 1.24 GHz has been achieved. The input sensitivity is -84 dBm exceeded the standards required by IEEE 802.16 has been observed.

Design of a 9 GHz CMOS low noise amplifier using gain-enhanced technique

In this article, a 9 GHz low noise amplifier (LNA) using gain-enhanced technique is presented. The compact and high-gain LNA with cascode topology is implemented in a standard 0.18-μm CMOS process. The gain-enhanced technique consists of two inductors in the common gate (CG) stage of the cascode configuration. The first inductor at the source terminal in the CG stage eliminates the parasitic effects caused by the parasitic capacitances of transistors at high frequencies. Moreover, the second inductor at the gate terminal in the CG stage achieves a negative resistance making a high gain characteristic of the amplifier. Finally, the measured small signal gain, noise figure and input P1dB at 9 GHz are 16.5 dB, 4.5 dB, and −15 dBm, respectively. The chip size of the compact LNA is 0.48 mm × 0.8 mm including all testing pads. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:479–481, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25778

Low Noise, High Gain LNA at 5.8GHz with Cascode andCascaded Techniques Using T-Matching Network forWireless Applications

This project presents a design of low noise, high gain LNA a 5.8 GHz with cascode and cascaded techniques using T-matching network is applicable for IEEE 802.16 standard. The amplifier use FHX76LP Low Noise SuperHEMT FET. The LNA designed used T-matching network consisting of lump element reactive element at the input and the output terminal. The cascode and cascaded low noise amplifier (LNA) produced gain of 36.8dB and noise figure (NF) at 1.3dB. The input reflection (S11) and output return loss (S22) are -11.4dB and -12.3dB respectively. The bandwidth of the amplifier is more than 1GHz. The input sensitivity is compliant with the IEEE 802.16 standards.

68–110-GHz-Band Low-Noise Amplifier Using Current Reuse Topology

This paper proposes a new topology for a broadband low-noise-amplifier (LNA). A common-gate (CG) amplifier with a matching inductor composes a unit cell, and the unit cells are cascaded to increase gain. As both the input and output impedances of the unit cell are matched to 50 Ω for a wide frequency range, it is possible to increase the gain while maintaining wide bandwidth. Thus, high-gain and broadband performance can be obtained using this topology. The other features of the amplifier are its small size, low power consumption, and current reuse topology. This paper presents the design methodology of a multistage CG amplifier with a matching inductor. Fabricated in an 80-nm InP HEMT process, we developed an ultra-broadband LNA. The LNA with a three-stage CG amplifier exhibited a gain of 18 dB and a noise figure of 3.5 dB from 68 to over 110 GHz. The power consumption was 12 mW under a power supply voltage of 3 V. The chip size is 0.55 × 0.75 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Furthermore, we developed a receiver for passive millimeter-wave imagers by integrating a six-stage LNA with a power detector. The chip size of the receiver is 1.1 × 0.75 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The sensitivity of the pre-amplified detector was more than 2 000 V/mW from 75 to 100 GHz. These results show that the topology is one of the best candidates for high-gain and broadband LNA with small size and low power consumption.