High Frequency Capacitance-voltage Characteristics Research Articles

Changes in the structural and electrophysical properties of Ba0.8Sr0.2TiO3 films with decreasing thickness

Abstract Comparative studies of structural and electrophysical properties were performed for Ba0.8Sr0.2TiO3 (BSTO) films with the thickness of 100 nm, 120 nm and 350 nm. The surface morphology, the domain structure and local polarization switches were explored in the ferroelectric phase whereas high-frequency capacitance–voltage characteristics were measured in the paraelectric phase at 121°С. It was shown that good crystalline properties of the BSTO surface and grains are preserved until the thickness of ceramic layers decrease to 100 nm. The surface roughness did not exceed 2 – 4 nm and the average radius grains was in the range of 64 – 87 nm. Polarization domains induced with a microscope tip were stable and are conserved for several hours. Electrophysical properties of Ba0.8Sr0.2TiO3 films in the paraelectric phase strongly depend on the thickness of layers of BSTO ceramics. Effective dielectric permittivity of BSTO in the limit of weak fields decreases when the film thickness decreases from 350 nm to 100 nm from 920 to 400.

Electrophysical Properties Investigation of Ba0.8Sr0.2TiO3 Ferroelectric Films in Paraelectric State

Phenomenological analytical expressions relating the ferroelectric film capacity to the coefficients of free energy decomposition in accordance to the degrees of substance polarization in paraelectric state are obtained. High-frequency capacitance-voltage characteristics of metal–Ba0.8Sr0.2TiO3–metal structures have been measured at the temperatures above the transition point from ferroelectric phase to paraelectric one. The comparison of theoretical and experimental data has been resulted in plotting the dependences of Ba0.8Sr0.2TiO3 film polarization on external voltage and determining the values of the parameters of the theory of phase transitions of second kind of Ginsburg–Landau for the objects under investigation.

Pre-Deposition Interfacial Oxidation and Post-Deposition Interface Nitridation of LPCVD TEOS Used as Gate Dielectric on 4H-SiC

In this work, the influence of pre-deposition interfacial oxidation or post-deposition interface nitridation on the performance of 4H-SiC MOS capacitors was investigated. The gate oxide was deposited by LPCVD using TEOS as a precursor. Interface breakdown strength was derived from leakage current and Time-Zero Dielectric Breakdown characteristics whereas interface quality was assessed by the determination of interface state density from the comparison of quasi-static and high frequency capacitance-voltage characteristics using high-low method. In the experimental results, it is demonstrated that the gate oxide deposited by LPCVD using TEOS which is post-deposition annealed in nitric oxide ambient is advantageous for trench-gate MOSFET due to its effectiveness for improving the interface quality and oxide reliability, whereas pre-deposition interfacial oxidation is deleterious to interface state density and breakdown strength.

Thermal and radiation response of 4H–SiC Schottky diodes with direct-write electrical contacts

A high-sensitivity 4H–SiC temperature sensor and an alpha detector have been fabricated using additively printed metal contacts. The surface morphology and electrical conductivity of the printed electrodes were established prior to Schottky diode development. 4H–SiC Schottky diodes with direct-write printed silver contacts on the 5 μm-thick epilayer on 4H–SiC were characterized electrically in terms of the forward and reverse current–voltage and high-frequency capacitance–voltage characteristics. The turn-on voltage of the Schottky diodes, as established from the forward current–voltage characteristics measured up to a temperature of 400 °C, showed a linear temperature dependence. Schottky diodes with direct-write printed Ag electrodes were able to measure alpha particles emitted from Americium-241. The high temperature and radiation response of the Schottky diodes show their suitability for multi-modal sensor fusion on the 4H–SiC platform for harsh environment applications.

Determination of the Parameters of Metal–Insulator–Semiconductor Structures with Ultrathin Insulating Layer from High-Frequency Capacitance–Voltage Measurements

A simple numerical method for processing the data of the high-frequency capacitance–voltage characteristics of metal–insulator–semiconductor structures is proposed. The approach is based on analyzing the experimental characteristics near the flat-band states, where the charge exchange of surface localized electron states is of little importance compared with changes in the near-boundary charged layer in the semiconductor. The developed technique makes it possible, first, to find the necessary parameters of the semiconductor and insulating layer and, second, to obtain the experimental field dependences of the energy-band bending in the semiconductor and the total concentration of the built-in charge, the charge of boundary states and minority charge carriers at the semiconductor–insulator interface in the range from the flat bands to deep depletion. The technique is well applicable to structures with an ultra-thin insulating layer. On n-Si-based metal–oxide–semiconductor samples with an oxide thickness of 39 A, experimental approbation of the proposed approach is carried out. The accuracy of the obtained results is 2–3%.

Определение параметров структур металл-диэлектрик- полупроводник со сверхтонким изолирующим слоем из высокочастотных вольт-фарадных характеристик

AbstractA simple numerical method for processing the data of the high-frequency capacitance–voltage characteristics of metal–insulator–semiconductor structures is proposed. The approach is based on analyzing the experimental characteristics near the flat-band states, where the charge exchange of surface localized electron states is of little importance compared with changes in the near-boundary charged layer in the semiconductor. The developed technique makes it possible, first, to find the necessary parameters of the semiconductor and insulating layer and, second, to obtain the experimental field dependences of the energy-band bending in the semiconductor and the total concentration of the built-in charge, the charge of boundary states and minority charge carriers at the semiconductor–insulator interface in the range from the flat bands to deep depletion. The technique is well applicable to structures with an ultra-thin insulating layer. On n -Si-based metal–oxide–semiconductor samples with an oxide thickness of 39 Å, experimental approbation of the proposed approach is carried out. The accuracy of the obtained results is 2–3%.

Generation of surface electron states with a silicon–ultrathin-oxide interface under the field-induced damage of metal–oxide–semiconductor structures

The high-frequency capacitance–voltage characteristics of metal–oxide–semiconductor structures on n-Si substrates with an oxide thickness of 39 A are studied upon being subjected to damage by field stress. It is shown that the action of a high, but pre-breakdown electric field on an ultrathin insulating layer brings about the formation of a large number of additional localized interface electron states with an energy level arranged at 0.14 eV below the conduction band of silicon. It is found that, as the field stress is increased, the recharging of newly formed centers provides the accumulation of excess charge up to 8 × 1012 cm–2 at the silicon–oxide interface. The lifetime of localized centers created under field stress is two days, after which the dependences of the charge localized at the semiconductor–insulator interface on the voltage at the gate after and before field stress are practically the same.

Photoluminescence of Ta2O5 films formed by the molecular layer deposition method

Ta2O5 films of different thicknesses (20–100 nm) synthesized by the molecular layer deposition method on p-type silicon substrates and thermally oxidized silicon substrates have been studied by the methods of high-frequency capacitance–voltage characteristics and photoluminescence. A hole-conduction channel is found to form in the Si–Ta2O5–field electrode system. A model of the electronic structure of Ta2O5 films is proposed based on an analysis of the measured PL spectra and performed electrical investigations.

High-Frequency Capacitance–Voltage Characteristics of N-Type Metal–Oxide–Semiconductor Capacitor Based on Strained-Si/SiGe Architecture

An accumulation metal–oxide–semiconductor (MOS) capacitor plays a key role in RF integrated circuits owing to its high linearity and independence of the operation frequency. The high-frequency capacitance–voltage (C–V) characteristics of a strained-Si/SiGe N-type MOS (NMOS) capacitor were studied to explain a measured behavior in which a “plateau” in the accumulation region was observed. By physically deriving the model of the NMOS capacitor, it was found that this plateau is substrate-doping-dependent and can also be strongly affected by the strained-Si layer thickness. The results from the model were compared with the experimental results and found to be in excellent agreement, indicating the validity of the model. The proposed model can provide valuable reference to the strained-Si device design and has been implemented in the software for extracting the parameter of a strained-Si MOSFET.

Bulk generation lifetime studies in semiconductor structures with nonuniform distribution of electrically active defects in silicon

A method for investigation of bulk generation lifetime of minority carriers τ g and their profiles in semiconductor of electron devices has been developed. It is based on combined application of dynamic unsteady-state current–voltage characteristics (DUCVC) and high-frequency capacitance–voltage characteristics (HFCVC) of metal–insulator–semiconductor (MIS) structures.The main advantage of DUCVC over other methods consists in higher sensitivity to registration of generation processes, possibility of direct determination of surface potential in MIS structures and experimental simplicity. Combined application of two kinds of stated characteristics eliminates doping concentration N d from τ g analysis in case of constant N d value in semiconductor. Thus the accuracy of τ g determination increases. If the doping concentration is constant and known, τ g is obtained only from DUCVC analysis. Bulk generation lifetime profiles have been investigated in Si–SiO 2 structures after formation of an internal getter near subsurface region of silicon. Effect of hydrogen annealings on formation of defect-free zone in silicon was investigated. Nonuniform distribution of electrically active defects (EAD) in silicon has been revealed.

Comparison of oxide leakage currents induced by ion implantation and high field electric stress

We compare in this work the electrical properties of gate leakage currents induced through the thin SiO2 oxide layer of metal-oxide-semiconductor structures by high-energy ion implantation (Boron B2+) and high field electrical stresses where electrons are injected from the gate in the Fowler–Nordheim regime. Even if the high-frequency capacitance–voltage characteristics are very different after both treatments, comparable increases and similar shapes are found at low field in static gate current–voltage curves, typical of equivalent oxide damage. Moreover, these stress or implantation induced leakage currents are both removed in a similar way by a thermal anneal under forming gas at 430°C. We conclude that similar defects could be induced through the oxide by both processes and generate those excess currents by a defect assisted tunneling mechanism.

Capacitance–voltage characteristics of selectively doped AlxGa1−xAs/GaAs heterostructures containing deep traps

The low- and high-frequency capacitance–voltage characteristics of a selectively doped AlxGa1−xAs/GaAs heterostructure containing deep traps in the AlxGa1−xAs layer are calculated. It is shown that the low-frequency capacitance–voltage characteristic features a rising portion when the deep traps are localized at the heterointerface, this rising portion being due to the onset of emptying of the deep traps. The calculated results agree with the experimental data.

Electrical characterisation of MNOS devices on p-type 6H-SiC

Metal-nitride-oxide semiconductor (MNOS), metal-oxide semiconductor (MOS) and metal-nitride semiconductor (MNS) devices have been fabricated on p-type 6H-SiC substrates without epitaxial layers. They have been characterised using high frequency capacitance-voltage (CV), conductance-voltage (GV) and current-voltage (IV) measurements. High frequency CV characteristics of SiC MNOS structures exhibit a capacitance-voltage behaviour that is very similar to high frequency CV characteristics of SiC MOS capacitors. Similar leakage current characteristics compared with p-type 6H-SiC MNS structures have been found for p-type 6H-SiC MNOS devices, but the SiO2/Si3N4 insulator current is lower, particularly for positive electric fields.

Silicon MIS structures using samarium oxide films

MIS structures Al–Sm 2O 3–Si were formed by vacuum evaporation of the rare earth element on silicon wafer and by thermal oxidation of the rare earth metal layer in the air at a temperature of 500–550°C. The current–voltage characteristics and temperature dependence of current were measured using direct current. The surface with silicon was determined using the method of high-frequency capacitance–voltage characteristics. The barrier energies on the interfaces Al–Sm 2O 3 (2.88–2.92 eV) Ni–Sm 2O 3 (3.28–3.32 eV), Si–Sm 2O 3 (2.69–2.72 eV) were evaluated from the spectral characteristics of photocurrent by the threshold to internal electron emission and from the dependence of photocurrent on the bias applied to the structure. The main characteristics of photo-injection current and charge trapping in MIS structures with samarium oxide film are described.

Improvement in buried silicon nitride silicon-on-insulator structures by fluorine-ion implantation

As an effort to improve buried Si3N4–Si interfaces in silicon-on-insulator (SOI) structures, fluorine was implanted either before or after the synthesis of buried silicon nitride layers by high dose nitrogen ion implantation. In these synthesized SOI structures, the thickness of Si overlayer and the buried silicon nitride layer was found to be 2400±25 and 1725±25 Å, respectively. Auger electron spectroscopy depth profile analysis illustrates that the fluorine ion implantation in the SOI structures modifies the distribution of nitrogen that results in better stoichiometry of the buried silicon nitride layers and abrupt Si3N4–Si interfaces. Current–voltage and high frequency capacitance–voltage characteristics were measured, and electrical breakdown measurements were performed on metal-nitride-silicon (MNS) structures, fabricated after removing the Si overlayer in the SOI structures. In the fluorine-implanted SOI specimens, the buried Si3N4 layers show a higher breakdown field strength of 4.4–5.2 MV/cm as compared to 3.5–4.0 MV/cm in the nonfluorine-implanted one. The capacitance–voltage analysis of the MNS capacitors reveals that the buried Si3N4–Si substrate interface exhibits a better quality with reduced fixed insulator charge and interface state densities after the fluorine ion implantation. Midgap interface state density at the buried Si3N4–Si substrate interface was as low as 1.48×1011 cm−2 eV−1 after the fluorine implantation, which is comparable to that of silicon nitride films deposited on silicon by the conventional low pressure chemical vapor deposition technique. The role of fluorine in improving the basic electrical properties of these SOI structures has been discussed.

Silicon metal-dielectric-semiconductor varicaps with an yttrium oxide dielectric

This paper reports an investigation of the electrophysical properties of metal-dielectric-semiconductor varicaps with an yttrium oxide dielectric, prepared by resistive vacuum evaporation of the rare-earth metal with subsequent thermal oxidation of the film in air at 500–550 °C. It is found that the electrical conductivity of the samples follows the Poole-Frenkel law. High-frequency capacitance-voltage characteristics are used to determine the specific capacitance of the dielectric, C0=0.027–0.03 μF/cm2, the slope of the capacitance-voltage characteristic, dC/dV=35–40 pF/V, the fixed charge in the dielectric, Qf=(1.7−2.7)×10−8 C/cm2, and the density of surface states at the flat-band potential, Nss=(1−2)×1011 cm−2·eV−1. The capacitance tuning range factor for the metal-dielectric-semiconductor varicaps is 2.5–3. These structures are shown to be applicable as metal-dielectric-semiconductor varicaps with a low control voltage and a high quality factor.

Heterojunctions of solid C70 and crystalline silicon: Rectifying properties and barrier heights

Heterojunctions of solid C70 and n- or p-type crystalline Si have been made. Current–voltage measurements show that both C70/n-Si and C70/p-Si contacts are rectifying but their directions of rectification are opposite to each other. Thermal activation measurements at a fixed forward bias show an exponential dependence of current on the reciprocal of temperature, from which we determine the effective barrier height as 0.23 eV for C70/n-Si and 0.27 eV for C70/p-Si. Relative dielectric constant of solid C70 was determined to be 4.96 through the study of high-frequency capacitance–voltage characteristics for Ti/C70/p-Si structures.

High frequency capacitance-voltage characteristics of MOS tunnel diodes in presence of interface states and fixed oxide charges

High frequency capacitance-voltage characteristics of MOS tunnel diodes in presence of interface states and fixed oxide charges

The influence of annealing on the capacitance-voltage characteristics of metal/SIPOS/silicon capacitors

Semi-insulating polycrystalline silicon (SIPOS)/Si samples have been annealed in forming gas at temperatures ranging from 300°C to 900°C. The influence of the anneal on the high frequency capacitance voltage characteristics of metal/SIPOS/silicon capacitors built afterwards has been studied. Up to annealing temperatures of 500°C, the rate of change of capacitance with voltage increases, while a decrease of this rate of change is observed at higher temperatures. Furthermore, the capacitance-voltage curves are shifted along the voltage axis towards more positive values up to 700°C. At higher annealing temperatures a shift in the opposite direction occurs.