High Forward Bias Research Articles

Analysis of Forward Bias Degradation Reduction in 4H-SiC PiN Diodes on Bonded Substrates

Analysis of forward bias degradation reduction of 4H-Silicon Carbide (4H-SiC) PiN diodes on bonded substrates was performed. In the analysis, cathodoluminescence (CL), photoluminescence imaging (PL imaging), and transmission electron microscope (TEM) were used. Under high forward bias stress, the Shockley-type stacking fault (SSF) does not expand into the transferred layer of the bonded substrate, while in the monocrystalline substrate, the SSF expands below the epilayer/substrate interface. The basal plane dislocation (BPD) within the transferred layer does not expand to the SSF. The transferred layer has the effect of suppressing the expansion of SSFs. This effect can be caused by hydrogen implantation for wafer splitting to produce bonded SiC substrates.

Effects of athermal carrier injection on Co-60 gamma-ray damage in SiC merged-PiN Schottky diodes

Co-60 gamma irradiation of SiC merged-PiN Schottky (MPS) diodes up to fluences of 1 Mrad (Si) produces increases in both forward and reverse current, with less damage when the devices are biased during irradiation. Subsequent injection of minority carriers by forward biasing at 300 K can partially produce some damage recovery, but at high forward biases also can lead to further degradation of the devices, even in the absence of radiation damage. Recombination-enhanced annealing by carrier injection overall is not an effective technique for recovering gamma-induced damage in SiC MPS diodes, especially when compared to other near athermal methods like electron wind force annealing.

On the Voltage Dependent Series Resistance, Interface Traps, and Conduction Mechanisms in the Al/(Ti-doped DLC)/p-Si/Au Schottky Barrier Diodes (SBDs)

In this study, Al-(Ti:DLC)-pSi/Au Schottky barrier diode (SBD) was manufactured instead of conventional metal / semiconductor (MS) with and without an interlayer and then several fundamental electrical-characteristics such as ideality factor (n), barrier height B series and shunt resistances (Rs, Rsh), concentration of acceptor atoms (NA), and width of depletion-layer (Wd) were derived from the forward-reverse bias current/voltage (I-V), capacitance and conductance as a function of voltage (C/G-V) data using various calculation-methods. Semi logarithmic IF-VF plot shows a linear behavior at lower-voltages and then departed from linearity as a result of the influence of series resistance/Rs and organic-interlayer. Three linear regions can be seen on the double-logarithmic IF-VF plot. with different slopes (1.28, 3.14, and 1.79) in regions with low, middle, and high forward bias, which are indicated that Ohmic-mechanism, trap-charge-limited-current (TCLC) mechanism, and space-charge-limited-current (SCLC) mechanism, respectively. Energy dependent surface states (Nss) vs (Ess-Ev) profile was also obtained from the Card-Rhoderick method by considering voltage-dependence of n and B and they were grown from the mid-gap energy up to the semiconductor's valance band (Ev). To see the impact of Rs for 1 MHz, the measured C/G-V graphs were amendment. All results are indicated that almost all electrical parameters and conduction mechanism are quite depending on Rs, Nss, and calculation method due the voltage dependent of them.

Evaluation of p-GaN HEMTs degradation under high temperatures forward and reverse gate bias stress

In this study, the degradation behavior and physical mechanism of the p-GaN HEMT devices under high-temperature gate bias (HTGB) with +5 V and −5 V were investigated. The DC characteristics show that the device after forward HTGB stress exhibits an obvious negative threshold voltage (Vth ) shift, while the device after reverse HTGB exhibits a negligible shift. The following explanations could be given for the deterioration mechanism: a portion of the two-dimensional hole gas (2DHG) accumulated in the p-GaN layer at the p-GaN/AlGaN interface under long-term forward bias may fill the trap in the AlGaN layer through the tunneling effect. In addition, the drain-source on-resistance of the device had increased after +5 V HTGB stress, and a distinct decrease of accumulated capacitance was observed in the Cg -Vg curve. It indicates a degradation of the gate quality of the device after applying a forward-biased HTGB stress.

Gate leakage mechanisms of the AlGaN/GaN HEMT with fluorinated graphene passivation

The AlGaN/GaN high-electron-mobility transistor (HEMT) passivated by fluorinated graphene (FG) has been investigated. The performances of the HEMTs without passivation before and after F plasma treatment, with FG, Silicon nitride (SiNx), FG/SiNx passivation were contrasted. Compared with the HEMT without F plasma treatment and passivation, the gate leakage current decreases one and a half orders of magnitude after F plasma treatment and SiNx passivated, and four orders of magnitude after FG and FG/SiNx passivated. To study the leakage mechanisms, the temperature dependences of gate leakages have been tested at 323 K–473 K. Through analysis and fitting, the leakages are composed of three components, which are thermionic emission (TE) current, two-dimensional variable range hopping (2D-VRH) current, and Fowler–Nordheim tunneling (FNT) current. TE dominates in the high forward bias region. 2D-VRH dominates in low forward bias. And the chief leakage mechanisms at reverse bias are 2D-VRH and FNT. At 473 K, Schottky barrier height of the HEMT with FG passivation is 1.21 eV. The activation energy and the effective barrier height on the HEMT with FG passivation are 0.64 eV and 0.33 eV respectively. Furthermore, the reasons for the decrement of the gate leakage on the HEMT with FG and FG/SiNx passivation are the enhancement of Schottky barrier heights and augmentation of activation energy. And the improvement in gate leakages for the HEMT passivated by FG/SiNx mainly results from the effect of FG.

X-ray diffraction imaging of fully packaged n-p-n transistors under accelerated ageing conditions.

X-ray diffraction imaging was used to monitor the local strains that developed around individual n-p-n bipolar transistors within fully encapsulated packages under conditions of extremely high forward bias to simulate accelerated ageing. Die warpage associated with the packaging was observed to relax systematically as the polymer became viscous due to the temperature rise associated with the dissipation of heat in the transistor. The direct image size and intensity from the individual transistors were interpreted in terms of a model in which local thermal expansion is treated as a cylindrical inclusion of distorted material, contrast arising principally from lattice tilt. The extension of the thermal strain image along the emitter with increasing power dissipation was ascribed to the effect of current crowding in the emitter region. Weaker large-area contrast associated with the base-collector region was interpreted as arising from the smaller change in effective misorientation at the high X-ray energy of thermal lattice dilation in the base region.

Switchable Photoresponse Mechanisms Implemented in Single van der Waals Semiconductor/Metal Heterostructure.

van der Waals (vdW) heterostructures based on two-dimensional (2D) semiconducting materials have been extensively studied for functional applications, and most of the reported devices work with sole mechanism. The emerging metallic 2D materials provide us new options for building functional vdW heterostructures via rational band engineering design. Here, we investigate the vdW semiconductor/metal heterostructure built with 2D semiconducting InSe and metallic 1T-phase NbTe2, whose electron affinity χInSe and work function ΦNbTe2 almost exactly align. Electrical characterization verifies exceptional diode-like rectification ratio of >103 for the InSe/NbTe2 heterostructure device. Further photocurrent mappings reveal the switchable photoresponse mechanisms of this heterostructure or, in other words, the alternative roles that metallic NbTe2 plays. Specifically, this heterostructure device works in a photovoltaic manner under reverse bias, whereas it turns to phototransistor with InSe channel and NbTe2 electrode under high forward bias. The switchable photoresponse mechanisms originate from the band alignment at the interface, where the band bending could be readily adjusted by the bias voltage. In addition, a conceptual optoelectronic logic gate is proposed based on the exclusive working mechanisms. Finally, the photodetection performance of this heterostructure is represented by an ultrahigh responsivity of ∼84 A/W to 532 nm laser. Our results demonstrate the valuable application of 2D metals in functional devices, as well as the potential of implementing photovoltaic device and phototransistor with single vdW heterostructure.

Nanostructure film of Ch-diisoQ/Si for the enhancement of photoelectrical performance of organic/inorganic cells

Thin films of Au/Ch-diisoQ/p-Si/Au were prepared by vacuum thermal evaporating technique. The structure and morphology of Ch-diisoQ on the p-Si substrate were studied by the analysis of X-ray diffract pattern and atomic force microscopy. The dark current density-voltage characteristics were investigated at various temperatures ranging from 298 to 393 K. A thermionic emission mechanism dominates the current at low voltage. At high forward bias voltage, the space charge limited current controlled by exponential trap distribution was the dominant mechanism. The dependence of the reverse current density on various temperatures was expounded via Poole-Frenkel and Schottky effects. Depend on the capacitance-voltage characteristic, the carrier concentration values and the built-in voltage were evaluated at different temperatures. The photocurrent characteristics of Ch-diisoQ/p-Si heterojunctions under the illumination of 100 W/cm2 were discussed. The values of the short circuit current (Jsc), the open-circuit voltage (Voc), the fill factor (FF), and power conversion efficiency (η%) of Ch-diisoQ/p-Si heterojunctions were comparing with other related organic/inorganic heterojunctions.

Voltage Dependent Barrier Height, Ideality Factor and Surface States in Au/(NiS-PVP)/n-Si (MPS) type Schottky Barrier Diodes

Metal-Polymer-Semiconductor (MPS) Schottky Barrier Diodes (SBD) were manufactured and their basic electrical parameters were obtained by the measurement of the forward and reverse bias current-voltage (I-V) in the wide bias voltage range (±3V) to determine the voltage dependent effects on Nickel-Sulphur (NiS) doped Poly Vinyl Pyrrolidone (PVP) polymer interlayer. The saturation current (I0), zero-bias barrier height (ΦB0), rectifying rate (RR), ideality factor (n) and the real value of series - shunt resistances (Rs - Rsh) were calculated. The voltage dependent profile of n (V), ΦB(V), and Rs (V) were derived. The forward bias ln I-V plot of the MPS type SBD indicates a good rectifier behaviour and it has two distinctive linear parts with different slopes which correspond to low (0.288 ≤V ≤0.625 V) and moderate (0.672 ≤ V ≤ 0.960 V) bias voltages and then deviates from linearity due to Rs and interlayer at high forward bias voltages. Energy dependent profile of Nss was obtained from the forward bias I-V data by considering voltage dependent barrier height (ΦB) and n. Nss plot represents U-shape behaviour in the forbidden bandgap. The mean value of Nss was found at about 7.0x1012 eV-1 cm-2 and this value is in the acceptable limit for a semiconductor device and such lower values of Nss are the consequences of the passivation effect on the surface states.

Impact of Ex-Situ Heating on Carrier Kinetics in GaN/InGaN Based Green LEDs

Self-heating has long been recognized as one of the major factors for performance deterioration of III-Nitride light emitting diodes (LEDs) during prolonged operation at high current. We have emulated the impact of self-heating on carrier kinetics in InGaN based green LED ( ∼ 516 nm at 1 mA forward current) using temperature dependent current vs voltage (T-I-V) characteristics in forward and reverse bias, where the temperature is varied from room temperature (25 °C) to 200 °C. Measured T-I-V characteristics are analyzed in detail so as to understand the dominant recombination mechanisms at different bias regimes. It is inferred that at high forward bias, Auger recombination plays a significant role during the ex-situ heating of LEDs. An exponential increase in reverse leakage current beyond a certain high temperature is attributed to the carriers attaining adequate thermal energy to escape from the active region.

High‐Current‐Density Enhancement‐Mode Ultrawide‐Bandgap AlGaN Channel Metal–Insulator–Semiconductor Heterojunction Field‐Effect Transistors with a Threshold Voltage of 5 V

Enhancement‐mode ultrawide‐bandgap Al0.65Ga0.35N/Al0.4Ga0.6N metal–insulator–semiconductor heterojunction field‐effect transistors are demonstrated using fluorine‐plasma treatment for threshold voltage control and Al2O3 as gate dielectric. The device exhibits a threshold voltage of 5 V, a maximum drain current density of 105 mA mm−1, and a transconductance of 19 mS mm−1. In addition, the capability to achieve low off‐state current density at 3–4 × 10−9 mA mm−1, an exceptionally low gate leakage current density of 1.4 × 10−8 mA mm−1 even at a high forward gate bias of VGS = 12 V, and a current on/off ratio >1010 is shown. Small signal measurement shows that the device has a unity current gain cutoff frequency fT of 3.8 GHz and power gain cutoff frequency fmax of 4.5 GHz.

Electrical characterization of silicon nitride interlayer-based MIS diode

In this study, silicon nitride (Si3N4) thin film on p-type GaAs wafer was deposited by RF magnetron sputtering. The surface morphology of Si3N4/GaAs structure was analyzed by atomic force microscopy (AFM). The electrical characteristics of the fabricated Au/Si3N4/p-GaAs metal–insulator-semiconductor (MIS) diode were investigated by using current–voltage (I–V) measurements at room temperature. The electronic parameters such as ideality factor (n) and barrier height (Φbo) of the MIS diode were derived using thermionic emission (TE). The Φbo was also extracted from Norde method. The barrier height values obtained from both TE and Norde were found to be in harmony with each other. The interface state density (Nss) and series resistance (Rs) parameters of the MIS diode were determined from the measured I–V data. In addition, the dominant current conduction mechanisms of the MIS diode were also investigated by forward bias ln(IF) − ln(VF) and reverse bias ln(IR) − VR0.5 plot. At high forward bias, the current conduction was associated with the space charge limited current (SCLC). At reverse bias region, the current conduction was associated with the Schottky emission (SE).

The origin of anomalous peak and negative capacitance on dielectric behavior in the accumulation region in Au/(0.07 Zn-doped polyvinyl alcohol)/n-4H–SiC metal-polymer-semiconductor structures/diodes studied by temperature-dependent impedance measurements

Capacitance-voltage-temperature (C–V-T) and conductance-voltage-temperature (G/ω-V-T) measurements of an Au/(0.07 Zn-doped polyvinyl alcohol)/n-4H–SiC metal-polymer-semiconductor structure were obtained to study the effect of temperature and voltage on dielectric characteristics such as the dielectric constant (ϵ′, ϵ″), loss tangent (tan δ), electric modulus, and ac conductivity. The experimental results show that the temperature and the bias voltage have a strong effect on the values of C and G/ω. A peak value is observed in the C–V plot in the forward bias voltage region (1.8 V ≤ V ≤ 2.8 V), which then decreases to a negative value for all temperatures in the high forward bias voltage region (V ≥ 4 V); such weird behavior is known as negative capacitance. C reduces with rising temperature at high forward bias voltage until negative capacitance is reached. On the other hand, G/ω increases with temperature at sufficiently high forward bias. This behavior of C and G/ω can be attributed to an increase in the number of polarization carriers. All these results were obtained for various temperatures at low and high forward bias voltage (0.5 and 6 V), respectively, and show that C, G/ω, ϵ′, ϵ″, tan δ, σac, and M″ increase and M′ decreases at 0.5 V, whereas C, ϵ′, M′, and M″ increase and G/ω, ϵ″, tan δ, and σac decrease at 6 V. Thus, we can say that the dielectric characteristics and ac conductivity of the diode are affected by change of the applied voltage bias and temperature.

Experimental evaluation of interface states during time-dependent dielectric breakdown of GaN-based MIS-HEMTs with LPCVD-SiNx gate dielectric**Project supported by the National Key Research and Development Program of China (Grant No. 2017YFB0402800), the Key Research and Development Program of Guangdong Province, China (Grant Nos. 2019B010128002 and 2020B010173001), the National Natural Science Foundation of China (Grant Nos. U1601210 and 61904207), the Natural Science

We experimentally evaluated the interface state density of GaN MIS-HEMTs during time-dependent dielectric breakdown (TDDB). Under a high forward gate bias stress, newly increased traps generate both at the SiNx/AlGaN interface and the SiNx bulk, resulting in the voltage shift and the increase of the voltage hysteresis. When prolonging the stress duration, the defects density generated in the SiNx dielectric becomes dominating, which drastically increases the gate leakage current and causes the catastrophic failure. After recovery by UV light illumination, the negative shift in threshold voltage (compared with the fresh one) confirms the accumulation of positive charge at the SiNx/AlGaN interface and/or in SiNx bulk, which is possibly ascribed to the broken bonds after long-term stress. These results experimentally confirm the role of defects in the TDDB of GaN-based MIS-HEMTs.

Enhanced Non-Uniformity Modeling of 4H-SiC Schottky Diode Characteristics Over Wide High Temperature and Forward Bias Ranges

A practical model, adequate for full reproduction of inhomogeneous Schottky diodes' forward characteristics over wide high-temperature and bias ranges, is proposed. According to this p-diode model, the Schottky contact current is considered to flow through m parallel-connected internal diodes, each with stable, constant barrier height and specific series resistance (both main model parameters). The value of m, required to reproduce the entire electrical forward behavior of a non-uniform Schottky contact, is directly connected to a particular model parameter (p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ), used to define the inhomogeneity degree. The p-diode model was tested on forward characteristics measured for both Ni and commercial Ti Schottky diodes on 4H-SiC, which exhibited varying degrees of inhomogeneity. Excellent replication of experimental curves was achieved for all investigated samples, even those with obvious irregularities, such as “humps”, explained in the model by the series resistances' influence. In the case of m = 1, the proposed model does not produce identical results with the conventional model of a homogeneous Schottky contact if p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ≠ 0. The value of this parameter indicates how much of an inhomogeneous contact's area is essentially used for current conduction.

Surface Thermal and Electric charge of PN Diode Expose by Soft Radiation Flash Exposure

In this study present the effect of soft radiation flash exposure (SRFE) to forward bias current-voltage (I-V) of PN diode by using COMSOL simulation program. The results show surface thermal and electric change while expose by radiation with flash exposure technique. Series resistance (Rs) increase around 2 times and close to idea case after expose by radiation, the radiation will impact to bulk defect and reduce surface recombination. SRFE induce temperature on surface and deep into silicon bulk. The value of Rs increase with increase expose time. The changing of Rs becomes independent from radiation dose at high forward bias voltage.

Investigation of Dielectric Properties, Electric Modulus and Conductivity of the Au/Zn-Doped PVA/n-4H-SiC (MPS) Structure Using Impedance Spectroscopy Method

Abstract The 50 nm thickness Zn-doped polyvinyl alcohol (PVA) was deposited on n-4H-SiC semiconductor as interlayer by electro-spinning method and so Au/Zn-doped PVA/n-4H-SiC metal-polymer-semiconductor (MPS) structure were fabricated. The real and imaginary parts of the complex dielectric constant (ε′, ε′′), loss-tangent (tan δ), the real and imaginary parts of the complex electric modulus (M′, M′′) and ac electrical conductivity (σ ac ) behavior of this structure were examined using impedance spectroscopy method in a wide range of frequency (1 kHz–400 kHz) and voltage (−1 V)–(+6 V) at room temperature. The values of ε′, ε′′, tan δ, M′, M′′ and σ ac are determined sensitive to the frequency and voltage in depletion and accumulation regions. The values of ε′ and ε′′ decrease with increasing frequency while the values of M′ and σ ac increase. The peak behavior in the tan δ and M′′ vs. frequency curves was attributed to the dielectric relaxation processes and surface states (Nss ). The plots of ln (σ ac ) vs. ln (f) at enough high forward bias voltage (+6 V) have three linear regions with different slopes which correspond to low, intermediate and high frequencies, respectively. The dc conductivity is effective at low frequencies whereas the ac conductivity effective at high frequencies. According to experimental results, the surface/dipole polarizations can occur more easily occur at low frequencies and the majority of Nss between Zn-doped PVA and n-4H-SiC contributes to the deviation of dielectric behavior of this structure.

Electroluminescence from light-emitting devices based on erbium-doped ZnO/n-Si heterostructures: Enhancement effect of fluorine co-doping.

We report on erbium (Er) related electroluminescence (EL) in the visible and near infrared (NIR) regions from the light-emitting device (LED) based on the Er-doped ZnO (ZnO:Er)/n-Si isotype heterostructure formed by sputtering ZnO:Er film on n-Si/n+-Si epitaxial wafer. Herein, the ZnO:Er film exhibits n-type in electrical conduction. The aforementioned LED is electroluminescent only under sufficiently high forward bias with the negative voltage connecting to n+-Si substrate. Such forward bias enables the electrons from n-Si to enter into the ultra-thin SiOx (x ≤ 2) layer inherently existing between the ZnO:Er film and n-Si via Poole-Frenkel conduction mechanism and, subsequently, to drift into the ZnO:Er film thus becoming hot electrons, which impact-excite the Er3+ ions to emit characteristic visible and NIR light. Furthermore, the Er-related EL from the aforementioned LED can be significantly enhanced through adopting the strategy of co-doping F- ions into the ZnO host, which brings about twofold primary effects. Firstly, due to the atomic size compensation between F- and Er3+ ions, the ZnO crystal grains become larger to accommodate much more optically active Er3+ ions. Secondly, the partial substitution of F- ions for O2- ions around the Er3+ ion reduces the symmetry of pseudo-octahedral crystal field of Er3+ ion, thus increasing the probabilities of intra-4f transitions of Er3+ ions. We believe that this work sheds light on developing efficient silicon-based LEDs using the Er-doped oxide semiconductors.

Combined ab-initio and Schrödinger-Poisson simulation study of spontaneous and piezoelectric polarizations effects on I–V characteristics of ZnO/MgxZn1-xO heterostructures

We present a theoretical simulation study of spontaneous (Psp) and piezoelectric (Ppz) polarizations in ZnO/MgxZn1-xO heterostructures (HS) and their influence on electronic properties through Current-Voltage (I–V) characteristics investigation. By combining ab-initio and Schrödinger-Poisson simulations, we determine Psp and Ppz respective contributions in the formation of the huge internally built-in electric field (Eip≥1 MV/cm) and highly degenerate 2DEG (ns ≥ 1013cm−2) in 2D ZnO/MgxZn1-xO Quantum Well HS at x ≤ 0.4. 3D heterojunction (HJ) case was then studied by investigating the 2D/3D transition. Fundamental changes are found by tracking the effects of increasing ZnO interface active layer width (LW) above a critical value (hc). At LW ≥ hc, we find that in addition to interface 2DEG confined electrons, there is a 2DHG hole gas (ps ≈ nS) accumulating at the opposite side of the totally depleted i-ZnO interface layer, at a distance d ≈ hc away from HJ interface. The resulting 2DHG/i-ZnO/2DEG structure forms a polarization built-in p+-i-n+ Esaki-type tunnel junction at ZnO/MgxZn1-xO HJ interface. In agreement with some experimental data, our I–V simulations show typical behavior of dual junction consisting of low bias Eip(x)-controlled Esaki-like ZnO p+-i-n+ tunneling junction, embedded within interface region of a high forward bias potential barrier controlled 3D ZnO/MgxZn1-xO HJ.

Enhancement-mode AlGaN channel high electron mobility transistor enabled by p-AlGaN gate

This work exhibits the ability to shift the threshold voltage of an Al0.45Ga0.55N/Al0.3Ga0.7N high electron mobility transistor through the implementation of a 100 nm thick p-Al0.3Ga0.7N gate. A maximum threshold voltage of +0.3 V was achieved with a 3 μm gate length. In addition to achieving enhancement-mode operation, this work also shows the capability to obtain high saturated drain current (&amp;gt;50 mA/mm), no gate hysteresis, high ION,MAX/IOFF,MIN ratio of &amp;gt;109, and exceptionally low gate leakage current of 10−6 mA/mm even under high forward bias of Vgs = 8 V.