High Electron Mobility Transistor Process Research Articles

A new design approach of Rat-Race coupler based compact GaN HEMT power amplifier towards flat high efficiency over broadband

This paper presents a high efficiency Rat-Race Coupler based compact GaN HEMT power amplifier (PA) design over broadband for high power transmitter in wireless communication. The rat-race coupler integrated PA Compact design is proposed for the first time as per author best knowledge. The design methodology used a higher order two open stubs and a rat-race coupler (RRC) at input/output sections to control harmonics impedances. The RRC is used to enhance the i/o power, and efficiency over broadband, which provides a good insertion loss, and consumes the least power and non-crucial impedance bandwidth for the normalized frequency band of interest. As a proof of concept, a PA is fabricated using a monolithic microwave integrated circuit (MMIC) 0.15 µm gallium nitride high electron mobility transistor (GaN HEMT) process. The measured result shows that the designed PA achieves a flat power added efficiency (PAE) of 65 % − 74 %, output power (Pout) of 44.8 dBm − 46 dBm, and drain efficiency (DE) of 72 % − 85 %, over a record wide frequency of 1.8 GHz − 3.6 GHz, which is the highest one among all reported harmonic tuned PAs.

2–26.5 GHz GaN ultra‐wideband amplifier with over 2 W output power

AbstractA 2–26.5GHz broadband amplifier monolithic microwave integrated circuit (MMIC) based on the 0.15 μm GaN high electron mobility transistor process has been developed. The broadband amplifier adopts a two‐stage distributed amplifier cascade structure, which improves the gain of the broadband amplifier. Further, the capacitive coupling is used to improve the gain bandwidth product of the power amplifier. To improve the output return loss of the wideband amplifier, a tuning stub is introduced at the output of the circuit. The on‐wafer measurement results show that the amplifier has a gain greater than 18 dB, gain flatness less than ±1.4 dB, and saturated output power >35 dBm with a >13% power added efficiency in the whole band.

A 28 GHz GaN 6-Bit Phase Shifter MMIC with Continuous Tuning Calibration Technique.

A 28 GHz digitally controlled 6-bit phase shifter with a precision calibration technique in GaN high-electron mobility transistor (HEMT) technology is presented for Ka-band phased-array systems and applications. It comprises six stages, in which stages 1 and 2 for 5.625° and 11.25° are designed in the form of a switched-line circuit, and stages 3, 4, and 5 for 22.5°, 45°, and 90° are designed in the form of a switched-filter circuit. The final stage 6 for 180° is designed in a single-to-differential balun followed by a single-pole double-throw (SPDT) switch for achieving an efficient phase inversion. A novel continuous tuning calibration technique is proposed to improve the phase accuracy. It controls the gate bias voltage of off-state HEMTs at the stage 6 SPDT switch for fine calibration of the output phase. Fabricated in a 0.15 μm GaN HEMT process using a die size of 1.75 mm2, the circuit produces 64 phase states at 28 GHz with a 5.625° step. The experimental results show that the Root-Mean-Square (RMS) phase error is significantly improved from 8.56° before calibration to 1.08° after calibration. It is also found that the calibration does not induce significant changes for other performances such as the insertion loss, RMS amplitude error, and input-referred P1dB. This work successfully demonstrates that the GaN technology can be applied to millimeter-wave high-power phased-array transceiver systems.

A broadband low‐loss SPDT RF switch using a new off‐chip compensation technology

SummaryAn off‐chip compensation technology for low‐loss and broadband characteristics of radio frequency (RF) switches is proposed based on mathematical analysis of series shunt single pole double throws switches in this letter. This compensation technology can absorb the parasitic parameters of the switch Field Effect Transistor, improving the insertion loss and return loss of the switch as well as supporting higher bandwidth. To verify the design principle, a RF switch, using the SANAN GaAs 0.15 um pseudomorphic High Electron Mobility Transistors (pHEMT) process, and an off‐chip compensation network were designed and implemented. Specifically, after using an off‐chip compensation network, the measured bandwidth of switch has been expanded from 1.1–8.8 to 0.8–11 GHz, while the input and output return loss have also improved significantly.

A Highly Integrated C-Band Feedback Resistor Transceiver Front-End Based on Inductive Resonance and Bandwidth Expansion Techniques.

This paper presents a highly integrated C-band RF transceiver front-end design consisting of two Single Pole Double Throw (SPDT) transmit/receive (T/R) switches, a Low Noise Amplifier (LNA), and a Power Amplifier (PA) for Ultra-Wideband (UWB) positioning system applications. When fabricated using a 0.25 μm GaAs pseudomorphic high electron mobility transistor (pHEMT) process, the switch is optimized for system isolation and stability using inductive resonance techniques. The transceiver front-end achieves overall bandwidth expansion as well as the flat noise in receive mode using the bandwidth expansion technique. The results show that the front-end modules (FEM) have a typical gain of 22 dB in transmit mode, 18 dB in receive mode, and 2 dB noise in the 4.5-8 GHz band, with a chip area of 1.56 × 1.46 mm2. Based on the available literature, it is known that the proposed circuit is the most highly integrated C-band RF transceiver front-end design for UWB applications in the same process.

Design of a 2–18 GHz low noise amplifier MMIC with current reused topology

AbstractA 2–18 GHz ultra wideband low noise amplifier (LNA) is illustrated in this letter. The proposed LNA adopts a two‐stage structure, which is composed of a common source amplifying stage and a cascode amplifying stage. By combining band extension matching technique, current reused topology and active bias circuit, the LNA performs excellent in gain, noise figure, power consumption, and immunization against the fluctuation of voltage supply. The LNA is implemented with a 0.18‐μm GaAs pseudomorphic high electron mobility transistor process and has a compact chip area of 1.75 × 1 mm2. The dedicated LNA achieves a measured average gain of 20.7 dB with ±1.5 dB variation all over the ultra‐wide bandwidth of 2–18 GHz. It also has a measured noise figure of lower than 1.7 dB and a measured output 1 dB compression point of higher than 5 dBm in the operating frequency band. The LNA has a low direct current power dissipation of 100 mW under a 5 V voltage supply.

An S-band MMIC LNA in GaAs 0.15-μm pHEMT

The study adopts a monolithic microwave integrated circuit (MMIC) low-noise amplifier (LNA) applied in S-band was designed using ADS simulation software, GaAs 0.15-um pseudomorphic high electron mobility transistor (pHEMT) process. The LNA small signal gain is greater than 30.8 dB, gain flatness is ±0.45 dB, noise coefficient is less than 1.5 dB, input and output return loss is greater than 10 dB, and the chip area is 1.2*2.4 mm2. The low noise amplifier is composed of a two-stage cascade structure. Gain flatness, gain control, and bandwidth broadening are improved by RLC negative feedback network. The minimum noise coefficient circle and maximum gain circle are narrowed by adding negative feedback to achieve better noise coefficient and gain.

Analysis and Design of a Gain-Enhanced 1–20-GHz LNA With Output-Stage Transformer Feedback

A gain-enhanced technique with output-stage transformer feedback (OSTF) for the low-noise amplifiers is proposed in this brief. The transformer is realized by a pair of magnetically coupled microstrip lines between the drain and source stages, one of which acts as a series-peaking inductor and the other as a source degenerate inductor. By adjusting the length and gap of the magnetically coupled microstrip lines, the tuning of the gain in high frequency is realized. To verify the proposed OSTF gain-enhanced scheme, two LNAs with the same structure are designed, with one having OSTF and the other not. The gainenhanced wideband LNA with OSTF is fabricated in 0.15-GaAs pseudomorphic high-electron mobility transistor process. The total chip area, including input and output testing pads, is 1.24 mm2. The simulated results show excellent performance with a maximum gain improvement of 3-dB at 20 GHz. The measured results show that the gain-enhanced LNA has an average gain of 22.6 dB and a noise figure below 2 dB from 1 to 20 GHz, which are in good agreement with simulated ones.

A Wideband True Time Delay Circuit Using 0.25 µm GaN HEMT Technology.

This paper presents a wideband 4-bit true time delay IC using a 0.25 μm GaN HEMT (High-Electron-Mobility Transistor) process for the beam-squint-free phased array antennas. The true time delay IC is implemented with a switched path circuit topology using DPDT (Double Pole Double Throw) with no shunt transistor in the inter-stages to improve the bandwidth and SPDT (Single Pole Single Throw) switches at the input and the output ports. The delay lines are implemented with CLC π-networks with the lumped element to ensure a compact chip size. A negative voltage generator and an SPI controller are implemented in the PCB (Printed Circuit Board) due to the lack of digital control logic in GaN technology. A maximum time delay of ~182 ps with a time delay resolution of 10.5 ps is achieved at DC-6 GHz. The RMS (Root Mean Square) time delay and amplitude error are <5 ps and <0.6 dB, respectively. The measured insertion loss is <6.8 dB and the input and output return losses are >10 dB at DC-6 GHz. The current consumption is nearly zero with a 3.3 V supply. The chip size including pads is 2.45 × 1.75 mm2. To the authors' knowledge, this is the first demonstration of a true time delay IC using GaN HEMT technology.

A Brief Overview of the Rapid Progress and Proposed Improvements in Gallium Nitride Epitaxy and Process for Third-Generation Semiconductors with Wide Bandgap

In this paper, we will discuss the rapid progress of third-generation semiconductors with wide bandgap, with a special focus on the gallium nitride (GaN) on silicon (Si). This architecture has high mass-production potential due to its low cost, larger size, and compatibility with CMOS-fab processes. As a result, several improvements have been proposed in terms of epitaxy structure and high electron mobility transistor (HEMT) process, particularly in the enhancement mode (E-mode). IMEC has made significant strides using a 200 mm 8-inch Qromis Substrate Technology (QST®) substrate for breakdown voltage to achieve 650 V in 2020, which was further improved to 1200 V by superlattice and carbon-doped in 2022. In 2016, IMEC adopted VEECO metal-organic chemical vapor deposition (MOCVD) for GaN on Si HEMT epitaxy structure and the process by implementing a three-layer field plate to improve dynamic on-resistance (RON). In 2019, Panasonic HD-GITs plus field version was utilized to effectively improve dynamic RON. Both reliability and dynamic RON have been enhanced by these improvements.

Sub-1-mm2 GaN Doherty Power Amplifier With Compact Source and Load Networks for a Small Form-Factor Package

In this letter, a gallium nitride (GaN) Doherty power amplifier (DPA) occupying a sub-1-mm2 die area is presented. This small die with compact source network (CSN) and compact load network (CLN) can be fully packaged in a small form factor. Previous solutions have integrated all components into the die with complicated matching and bias networks, resulting in a large and expensive die area. Innovative component merging and compact bond-wire matching in the CSN and CLN have substantially reduced the die size for future massive multiple-input multipleoutput (MIMO) small cells. This proposed DPA was designed and fabricated using a commercial 150-nm GaN/silicon carbide (SiC) high electron mobility transistor (HEMT) process to validate architecture and design methodologies. Experimental results demonstrate that this sub-1-mm2 DPA can deliver saturated powers (Psat) of 38-39 dBm from 4.2 to 4.6 GHz. Measured drain efficiencies (DEs) of the proposed DPA are more than 45 %, from the 6-dB back off power to Psat, over the entire frequency band.

C-Band 30 W High PAE Power Amplifier MMIC with Second Harmonic Suppression for Radar Network Application.

In order to meet the application requirements of radar networks for high efficiency and high second harmonic suppression (SHS) of power amplifiers, this paper proposes a C-band 30 W power amplifier (PA) microwave monolithic integrated circuit (MMIC) based on 0.25 μm gallium nitride (GaN) high electron mobility transistor (HEMT) process. The proposed PA uses a two-stage amplifier structure to achieve high power gain. A topology with SHS is designed in the output-matching network. Besides, the large signal model load pull simulation and the harmonic control technology in the output stage are used to improve efficiency. The high-power additional efficiency (PAE) and high SHS of the PA MMIC are achieved simultaneously. In the 5-6 GHz frequency range, multiple indicator measurements of the proposed PA show that output power is over 45 dBm, the PAE is more than 57%, the SHS exceeds 45 dBc, the power gain is greater than 24 dB, which are conducted under the condition of 100 μs pulse width and 10% duty cycle. In addition, the size of the PA MMIC, including bonding pads, is 3.3 × 3.1 mm2.

The 3.4 GHz BAW RF Filter Based on Single Crystal AlN Resonator for 5G Application.

To meet the stringent requirements of 5G communication, we proposed a high-performance bulk acoustic wave (BAW) filter based on single crystal AlN piezoelectric films on a SiC substrate. The fabrication of the BAW filter is compatible with the GaN high electron mobility transistor (HEMT) process, enabling the implementation of the integration of the BAW device and high-performance monolithic microwave integrated circuit (MMIC). The single crystal AlN piezoelectric film with 650-nm thickness was epitaxially grown on the SiC substrate by Metal Organic Chemical Vapor Deposition (MOCVD). After wafer bonding and substrate removal, the single crystal AlN film with electrode layers was transferred to another SiC wafer to form an air gap type BAW. Testing results showed that the fabricated resonators have a maximum Q-factor up to 837 at 3.3 GHz resonant frequency and electromechanical coupling coefficient up to 7.2%. Ladder-type filters were developed to verify the capabilities of the BAW and process, which has a center frequency of 3.38 GHz with 160 MHz 3 dB bandwidth. The filter achieved a minimum 1.5 dB insertion loss and more than 31 dB out-of-band rejection. The high performance of the filters is attributed to the high crystallinity and low defects of epitaxial single crystal AlN films.

High-Performance RF Power Amplifier Module Using Optimum Chip-Level Packaging Structure

This article presents a high-performance radio frequency (RF) power amplifier (PA) module for which an optimum chip-level packaging structure is proposed to reduce the operating temperature of the RF PA monolithic microwave integrated circuit (MMIC). Because the output power ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) and the efficiency of an RF PA module are strongly affected by the thermal characteristics of the PA MMIC, various types of heat spreader materials and thermal interface materials have been examined to implement the PA chip-level packaging structure, and the optimum combination is proposed for a performance enhancement of the PA module in this article. In addition, the optimum form-factor of the heat spreader was suggested based on a thermal simulation. To verify the proposed PA chip-level packaging structure, a 10 W 6–18 GHz RF PA MMIC using a commercial 0.25- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m gallium nitride high electron mobility transistor process was designed and implemented for radar applications. The operating temperature of the PA MMIC on the proposed chip-level packaging structure shows a dramatic reduction of 24.8 °C, and accordingly, the average <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> and average power-added efficiency are enhanced by up to 9.2% and 2.8%, respectively, when compared with a PA module using the conventional chip-level packaging structure.

A Wideband High-Efficiency GaN MMIC Power Amplifier for Sub-6-GHz Applications.

The monolithic microwave integrated circuit (MMIC) power amplifiers serve an essential and critical role in RF transmit/receive (T/R) modules of phased array radar systems, mobile communication systems and satellite systems. Over recent years, there has been an increasing requirement to develop wideband high-efficiency MMIC high power amplifiers (HPAs) to accommodate wideband operation and reduce power consumption. This paper presents a wideband high efficiency MMIC HPA for Sub-6-GHz applications using a 0.25-μm gate-length D-mode GaN/SiC high electron mobility transistor (HEMT) process. The amplifier consists of two stages with two HEMT cells for the driver stage and eight HEMT cells for the power stage. To obtain a flat gain while maintaining the wideband characteristic, a gain equalization technique is employed in the inter-stage matching circuit. Meanwhile, a low-loss output matching network is utilized to ensure high efficiency. The fabricated HPA occupies a compact chip area of 14.35 mm2 including testing pads. Over the frequency range of 2–6 GHz, measured results of this HPA show a saturated continuous wave (CW) output power of 44.4–45.2 dBm, a power added efficiency (PAE) of 35.8–51.3%, a small signal gain of 24–25.5 dB, and maximum input and output return losses of 14.5 and 10 dB, respectively.

A Novel GaN-Based Metal-2DEG-Metal Varactor With Cutoff Frequency of 3.13 THz

A novel metal-2DEG-metal (M-2DEG-M) varactor based on GaN high electron mobility transistor (HEMT) structures was designed and investigated. The novel varactor employed metal-2DEG direct contacts to form two back-to-back Schottky junctions, eliminating the threshold voltage and showing a strong nonlinear <i>CV</i> behavior at zero bias, which was more beneficial to terahertz (THz) multiplier circuits design compared with the conventional metal&#x2013;semiconductor&#x2013;metal (MSM) 2DEG varactors. The metal-2DEG direct contacts reduced the junction capacitance and the series resistance simultaneously. For the M-2DEG-M varactor with an electrode length of <inline-formula> <tex-math notation="LaTeX">$1 \mu \text{m}$ </tex-math></inline-formula>, the device capacitance at zero bias was determined to be 3.0 fF (without de-embedding the parasitic component), with the series resistance of <inline-formula> <tex-math notation="LaTeX">$25.4 \Omega $ </tex-math></inline-formula>, resulting in a record high cutoff frequency of 2.09 THz for GaN-based varactors. After de-embedding the parasitic pad-to-pad capacitance, the cutoff frequency and figure of merit (FOM) would be 3.13 and 7.14 THz, respectively. Additionally, the whole fabrication process of the novel varactor only needed two steps of ordinary UV lithography without elaborate nanoscale T-gates, totally compatible with GaN-based HEMT process.

A 5.5/12.5‐GHz concurrent dual‐band power amplifier MMIC in 0.25 μm GaAs technology

A concurrent 5.5/12.5-GHz dual-band power amplifier (PA) is designed and implemented in a 0.25 μm GaAs pseudomorphic high electron mobility transistor process. The PA is composed of two stages and adopts LC parallel and series networks for dual-band matching. The efficiency of the PA is improved by lowering the drain voltage of the driver stage. Measurement results show that the proposed PA features the maximum small-signal gain of 17.1 and 15.6 dB, the maximum output power of 24.9 and 24.5 dBm, and peak power-added efficiency (PAE) of 35.5% and 35% at 5.5 and 12.5 GHz, respectively. The PA consumes a total DC of 73 mA, and its power consumption is 503 mW. The chip size of the PA is 1.4 × 1.3 mm2 including all testing pads.

A High-Efficiency 28 GHz/39 GHz Dual-Band Power Amplifier MMIC for 5G Communication

A high-efficiency 28 GHz/39 GHz concurrent dual-band power amplifier (PA) is proposed using the 90 nm GaAs pseudomorphic high-electron mobility transistor (pHEMT) process for the millimeter-waveband fifth generation (5G) communication application in this letter. Its high efficiency is achieved by adopting a low-loss dual-band output matching network (OMN) and employing a large power push ratio (3:1) for the driver stage and the output stage under the same bias voltage. The dual-band PA has the measured gain of 19.1 and 20.3 dB, as well as the power added efficiency (PAE) of 51.3&#x0025; with the 23.8-dBm output power and 49.5&#x0025; with the 23.7-dBm output power at the 3 dB compression point (<inline-formula> <tex-math notation="LaTeX">$P_{\mathrm {3\,dB}}$ </tex-math></inline-formula>), at 29.6 and 39 GHz, respectively. The area of the proposed dual-band PA is 1.45 mm <inline-formula> <tex-math notation="LaTeX">$\times1.2$ </tex-math></inline-formula> mm including pads.

Fabrication of 150‐nm AlGaN/GaN field‐plated High Electron Mobility Transistors using i ‐line stepper

This article reports a high throughput 150-nm-gate AlGaN/GaN high electron mobility transistor (HEMT) process using i-line stepper lithography and a thermal reflow technique. Optimizing thermal reflow conditions, fabrication of a 150-nm gate structure was successfully realized with the initial resist opening of 0.7 μm. AlGaN/GaN field-plated HEMTs were fabricated on a semi-insulating SiC substrate by using this process. In spite of unoptimized structures, fabricated 150-nm gate devices exhibited the maximum drain current of 0.65 A/mm and the gate-drain breakdown voltage exceeding 200 V. Based on cold HEMT extraction measurements, the average gate length of 187 nm and the standard deviation of 30 nm were obtained on a quarter 4-in. wafer.

Optimization of Oxygen Plasma Treatment on Ohmic Contact for AlGaN/GaN HEMTs on High-Resistivity Si Substrate

The oxygen plasma surface treatment prior to ohmic metal deposition was developed to reduce the ohmic contact resistance (RC) for AlGaN/GaN high electron mobility transistors (HEMTs) on a high-resistive Si substrate. The oxygen plasma, which was produced by an inductively coupled plasma (ICP) etching system, has been optimized by varying the combination of radio frequency (RF) and ICP power. By using the transmission line method (TLM) measurement, an ohmic contact resistance of 0.34 Ω∙mm and a specific contact resistivity (ρC) of 3.29 × 10–6 Ω∙cm2 was obtained with the optimized oxygen plasma conditions (ICP power of 250 W, RF power of 75 W, 0.8 Pa, O2 flow of 30 cm3/min, 5 min), which was about 74% lower than that of the reference sample. Atomic force microscopy (AFM), energy dispersive X-ray spectroscopy (EDX), and photoluminescence (PL) measurements revealed that a large nitrogen vacancy, which was induced near the surface by the oxygen plasma treatment, was the primary factor in the formation of low ohmic contact. Finally, this plasma treatment has been integrated into the HEMTs process, with a maximum drain saturation current of 0.77 A/mm obtained using gate bias at 2 V on AlGaN/GaN HEMTs. Oxygen plasma treatment is a simple and efficient approach, without the requirement of an additional mask or etch process, and shows promise to improve the Direct Current (DC) and RF performance for AlGaN/GaN HEMTs.