High Drain Current Density Research Articles

A systematic study on the efficacy of low-temperature GaN regrown on p-GaN to suppress Mg out-diffusion

Embedding p-type gallium nitride (p-GaN) in AlxGa1-xN-based thin films has garnered significant interest as a versatile structure for bandgap engineering such as tunnel/super-junctions or current blocking/guiding functions in electronic devices. However, Mg, a p-GaN dopant, has an undesirable diffusive capacity into the nearby thin films at a high growth temperature (>1,000°C), resulting in structural challenges in device design. This study systematically investigated the low-temperature GaN (LT-GaN) layer regrown on p-GaN that suppresses Mg diffusion according to metal–organic chemical vapor deposition growth conditions. Prototype Al0.3Ga0.7N (40 nm)/GaN (140 nm) high-electron-mobility transistors (HEMTs) were regrown with LT-GaN on p-GaN (300 nm), and a high two-dimensional electron gas (2DEG) density of 3.13E12 cm−2 was achieved by inserting a 100-nm-thick LT-GaN layer grown at 750°C; in contrast, only 1.76E10 cm−2 2DEG density was obtained from Al0.3Ga0.7N/GaN HEMTs regrown directly on p-GaN (Mg: 4.0E19 cm−3). The fabricated Al0.3Ga0.7N/GaN HEMTs with 100-nm-thick LT-GaN demonstrated a high drain current density of 84.5 mA/mm with a low on-state resistance of 31 Ω·mm. The AlxGa1-xN/LT-GaN/p-GaN platform demonstrated here paves the way for various III-nitride-based structures with embedded p-GaN.

Dependence of Device Performances on Fin Ratios of AlGaN/GaN Nanoscale Fin-HEMTs

In this article, we report the fabrication and characterization of AlGaN/GaN fin-type high electron mobility transistors (Fin-HEMTs) grown on high-resistance silicon substrates. The Fin-HEMTs have a gate length of 125 nm by using electron-beam lithography with various fin ratios, which are defined as the total effective periodic gate widths over the gate width, along the whole gate width. The Fin-HEMTs are designed with three fin ratios of 0.5, 0.3, and 0.25. The on-resistance decreases with reducing the fin ratio and reaches 1.1 Ω mm at the fin ratio of 0.25. In addition, the Fin-HEMT with a fin ratio of 0.25 still exhibits a 14% higher drain current density than the planar device. With tetramethylammonium hydroxide (TMAH) etching, the current collapse caused by surface traps on the fin’s sidewalls is significantly reduced from 28.9% to 2.4% by the pulse I-V measurement. The Fin-HEMTs also can improve the gate control capability through the analyses of small-signal and large-signal measurements.

Indium Zinc Oxide Nanosheet Transistor With 2 nm Channel Thickness for Monolithic Three-Dimensional Integrated Circuit

We have successfully fabricated an amorphous indium zinc oxide (a-IZO) thin film transistor (TFT) with a 2 nm-thick nanosheet channel, which demonstrated an impressive mobility of 84 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V-s. By shrinking the channel length and width, the a-IZO TFT exhibited a high drain current density of 1.6 mA/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> = 1V, a sharper subthreshold swing of 72 mV/dec, and better drain-induced barrier lowering (DIBL) of 94 mV/V. By integrating p-type low-temperature poly-Si (LTPS) TFT and n-type a-IZO TFT, we have designed a heterogeneous complementary inverter that can achieve a high voltage gain of 99 V/V, while consuming only a few picowatts of power at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1.5 V. All thermal budgets used in this study are compatible with the back-end-of-line (BEOL) process, making it a suitable approach for fabricating monolithic three-dimensional integrated circuits (M3D-ICs).

Design and analysis of normally-off GaN-HEMT using β-Ga2O3 buffer for low-loss power converter applications

An enhancement mode HETM with β-Ga2O3 buffer is proposed, and its electrical characteristics are analyzed using the physics-based numerical simulator ATLAS TCAD. HEMT with p-GaN/AlGaN/GaN/β-Ga2O3 utilized for normally-off mode operation of HEMT. The proposed β-Ga2O3 buffer based HEMT in this work reveals low on-resistance (Ron), high drain current density (IDS,max), high transconductance (gm,max), excellent breakdown voltage (VBR) and low gate switching delay. The ultra-wide bandgap β-Ga2O3 (EG ∼ 4.7 eV) buffer on silicon carbide (SiC) substrate HEMT mitigates the interface-related traps due to nearly lattice match with GaN and suppressing buffer leakage current by serving as a natural back-barrier. This β-Ga2O3 back-barrier structure increases the 2DEG (two-dimensional electron gas) and mitigates buffer leakage currents. Numerical simulation shows IDS,max of 0.95 A/mm, Ron of 4.26 Ω mm, and VBR of 835 V. for LG = 0.8 μm HEMT. The excellent device characteristics indicate the merits of β-Ga2O3 buffer-based normally-off HEMT for medium voltage range (<800 V) low resistive loss power converters applications.

DC and RF performance of HR Si(111)-based AlGaN/GaN MIS-HEMT with a symmetrical multi-finger grid array structure for 5G N28 700MHz low-bias-control applications

HR Si(111)-based AlGaN/GaN metal insulator semiconductor high electron mobility transistor (MIS-HEMT) for 5G mobile communication at N28 700 MHz band is proposed in this paper. The device is ingeniously designed with a symmetrical dual-column multi-finger grid array structure. In addition, the device is designed with an MIS gate with a 6 nm SiN dielectric film to suppress the leakage current and a source field plate to suppress the current collapse effect. The fabrication process of the device is studied in detail, including the epitaxial surface treatment, F ion implantation isolation, ohmic contact, electron beam lithography gate process, surface passivation, and source field plate. A device with a gate length of 0.25 μm, gate-source space of 1 μm, a gate width of 1200 μm (the number of gate fingers is 12 with a single-finger gate width of 100 μm), and source field plate length of 0.2 μm is fabricated successfully. Results of electrical tests show that the HEMT device has a threshold voltage of about −7.5 V, a low knee voltage of about 4 V, a high saturation drain current density of 750 mA/mm, and a gate leakage current as low as less than 160 pA at the gate bias of 0 V. At the frequency band of 703–803 MHz, with low bias control of 10 V, the S21 of HEMT is about 5.923–7.261 dB, the gain flatness is 1.338 dB, the current gain is about 27.3 dB, and the stability factor is more than 1. This device would be a good candidate for future 5G low-frequency and low-voltage-control applications.

Scaling Study on High-Current Density Low-Dispersion GaN Vertical FinFETs

GaN vertical FinFETs on a bulk GaN substrate were fabricated with various fin widths and 400 ns pulsed I-V measurements were performed to investigate their self-heating and DC-RF dispersion. With low-temperature post-gate processes including Ar plasma-enhanced Ohmic contact, a high drain current density (>175 kA cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–2</sup> ) and a low gate leakage (<1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–7</sup> kA cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–2</sup> ) could be achieved simultaneously. When normalized by the active fin area, the specific on-resistance was 0.030mΩcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at the drain on-current of 119 kA cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–2</sup> for the 300nm fin-width single-finger device. A 25-finger device with the same fin width and fin-to-fin pitch of 3 μm showed the on-resistance of 0.043mΩcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (0.43mΩcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> when normalized by the total device area of 6000 μm2), which was one of the lowest values reported. Low DC-RF dispersion was observed for the devices more than 2.5mm away from the wafer edge. This study also reports that more influence of self-heating was observed as the fin width scaled down or the number of fingers increased.

Demonstration of self-aligned β-Ga2O3 δ-doped MOSFETs with current density &amp;gt;550 mA/mm

We report on the design and fabrication of β-Ga2O3 self-aligned lateral MOSFETs by utilizing a heavily doped β-Ga2O3 cap layer. The fabrication of the self-aligned device used a combination of in situ Ga etching for damage free gate recess, in situ growth of Al2O3 for gate dielectric, and atomic layer deposited Al2O3 based sidewall spacers to form highly scaled (&amp;lt;100 nm) source–gate and gate–drain access regions. The fabricated device showed a record high DC drain current density of 560 mA/mm at a drain bias of 5 V. The DC current density was found to be limited by excessive self-heating resulting in premature current saturation in the device. Pulsed I–V measurements of the device showed a record high current density of 895 mA/mm and a high transconductance of 43 mS/mm, thanks to reduced self-heating in the device. The high current densities obtained in this work are promising for the development of high power density devices based on β-Ga2O3.

875-MW/cm² Low-Resistance NO₂ p-Type Doped Chemical Mechanical Planarized Diamond MOSFETs

In this study, an Al₂O₃ passivated, NO₂ p-type doped diamond metal&#x2013;oxide&#x2013;semiconductor field-effect transistor (MOSFET) was fabricated on a chemical mechanical planarized high-quality heteroepitaxial diamond (Kenzan diamond^&#x00AE;) substrate. This MOSFET exhibited a low specific ON-resistance of 7.54 <inline-formula> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula>cm² and a high OFF-state breakdown voltage of &#x2212;2568 V. The chemical mechanical planarization (CMP) was performed for 200 h on the diamond surface which effectively removed the subsurface damages resulting in a low resistive diamond surface. Thus, the MOSFET showed a high drain current density of &#x2212;0.68 A/mm and a maximum available power density (Baliga&#x2019;s figure-of-merit) of 874.6 MW/cm²&#x2014;the highest reported value for diamond devices.

Improved on-state performance in AlGaN-channel heterojunction field-effect transistors with a quaternary AlGaInN barrier layer and a selectively grown n++-GaN contact layer

Al0.19Ga0.81N-channel metal-insulator-semiconductor heterojunction field-effect transistors (MIS-HFETs) with a quaternary AlGaInN barrier layer and a selectively regrown n++-GaN contact layer were fabricated using the self-alignment selective-area growth (SAG) technique. The self-alignment SAG process was accomplished by the local-area etching process and the subsequent refilling process with a highly-Si-doped n++-GaN layer by metalorganic chemical vapor deposition (MOCVD). It was confirmed that the ohmic contact resistance was drastically reduced from 10.5 Ωmm to 2.5 Ωmm via the self-alignment SAG contacts. Further, fabricated MIS-HFETs with a gate length of 1.5 μm and a drain-to-source length of 9.5 μm exhibited a high drain current density of over 300 mA/mm with a drain-to-source resistance of approximately 25 Ω mm. The fabricated devices also showed a high off-state breakdown voltage of 1220 V at a gate-to-drain length of 10 μm, corresponding to a breakdown field of 122 V/μm.

C–Si bonded two-dimensional hole gas diamond MOSFET with normally-off operation and wide temperature range stability

A C–Si bonded SiO2/diamond interface is formed under a SiO2 mask during the selective diamond growth at a high temperature in a H2 atmosphere including methane (5%). A few monolayers with C–Si bonding at the SiO2/diamond surface are confirmed through X-ray photoelectron spectroscopy at the C1s and Si2p core levels from 290 eV to 271 eV and 107 eV–95 eV, respectively. In addition, secondary ion mass spectroscopy results suggest that the C–Si bonds, and not C–H bonds, are majority at the interface and are mainly responsible for the field effect transistor (FET) operation. Two-dimensional hole gas C–Si diamond metal–oxide–semiconductor FET (MOSFETs) are fabricated using the C–Si diamond sub-surface as a p-channel. The MOSFETs in which the actual length from the source to the drain (LSD) is 12 μm–6 μm show appreciable field-effect mobility (e.g. 140 cm2V−1s−1 at LSD = 12 μm and 300 K) and normally-off operation. The wide temperature characteristics of the C–Si MOSFETs are confirmed and the device shows high stability, and a high on/off ratio of 106 is maintained at 673 K. The C–Si bonding at the SiO2/diamond interface provide a lower interface state density which makes the MOSFET show high drain current density and field-effect mobility with normally-off operation.

145-MW/cm2 Heteroepitaxial Diamond MOSFETs With NO2 p-Type Doping and an Al2O3 Passivation Layer

In this study, we investigated diamond metal oxide semiconductor field effect transistors (MOSFETs) with NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> p-type doping and Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> passivation layer fabricated on a high-quality heteroepitaxial single crystal (001) diamond substrate called Kenzan diamond <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> . MOSFETs with a gate length of 1.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> and nearly zero source-gate spacing exhibited a high drain current density of −776 mA/mm with a negligible gate leakage current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt; 0.1~\mu \text{A}$ </tex-math></inline-formula> /mm). MOSFETs with a gate-to-drain length of 4.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> delivered a high off-state breakdown voltage (−618 V) at an average breakdown field of 1.2 MV/cm and a specific on-resistance of 2.63 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Baliga’s Figure-Of-Merits was calculated as 145 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the anticipated maximum power density was 12 W/mm. The diamond MOSFET was improved with high crystal quality.

High performance CsPbBr3 perovskite nanocrystal vertical phototransistor with graphene electrode

All-inorganic cesium lead halide perovskites (CsPbX3, X = Cl, Br, and I) nanocrystals (NCs) have been extensively studied as optically active materials in photodetectors, light-emitting diodes, solar cells and lasers, in view of their combination of the outstanding characteristics of perovskites and NCs such as low cost, solution processability, bandgap tunability, and large absorption coefficient. Here we report the fabrication of graphene electrode based CsPbBr3 NCs vertical field-effect phototransistor (VFEPT), exhibiting high photoelectrical performances benifiting from the ultrashort channel, the high ultraviolet–visible absorption of CsPbBr3 NCs, and the adjustable Fermi level of graphene. The VFEPT exhibited high drain current density of 0.25 A/cm2 for p-type and 0.2 A/cm2 for n-type transports in dark condition. The responsivity, effective quantum efficiency and detectivity reached as high as 2.2 × 103 A/W, 6.7 × 105%, 1.1 × 109 Jones at an irradiance power of 342 mW/cm2 under 405 nm illumination. Additionally, the device showed excellent stable and reproducible dynamic response to cyclical optical signal, with the rise and decay time as fast as 20 ms/36 ms. The device described here has great potential applications in high-sensitivity, high-speed, and low-power nanometer-scale photodetectors.

200°C normally off AlGaN/GaN MISFET with 321 mA/mm drain current density and 1055 V breakdown voltage

A high-performance normally off recess-gated aluminium gallium nitride (AlGaN)/GaN metal–insulator–semiconductor field-effect transistor (MISFET) is successfully demonstrated with operation temperature of 200°C which was fabricated by using a self-terminating gate recess etching technique. At 200°C, by employing a high-quality aluminium oxide/silicon nitride bilayer as gate dielectrics, the fabricated device exhibits a high threshold voltage of 4.5 V, a high drain current density of 321 mA/mm, a low off-state leakage current of 20 μA/mm as well as a high on/off current ratio of ∼106. Furthermore, a high forward gate breakdown voltage of 23.6 V (∼7.9 MV/cm) and an off-state breakdown voltage as high as 1055 V are obtained in the fabricated device, both of which, as far as it is known, is the highest reported value in normally off GaN devices operated at 200°C. The high threshold voltage, large drain current density, low off-state leakage current, high gate breakdown voltage as well as high off-state breakdown voltage make this normally off recess-gated AlGaN/GaN MISFET very suitable for high-temperature power switch applications.

Radiofrequency performance of hydrogenated diamond MOSFETs with alumina

Hydrogenated diamond MOSFETs with self-oxidized alumina as a gate dielectric are fabricated. The diamond MOSFETs show a high maximum drain current density of 466 mA/mm at VGS = −6 V, a transconductance of 58 mS/mm, and an off-state breakdown voltage of −53 V. The maximum output power density reaches 745 mW/mm at 2 GHz continuous wave, which is the highest reported value for diamond transistors measured at 2 GHz. The output power value measured is lower than that estimated. Pulse I-V analysis shows that the main factor that affects the output power of the diamond MOSFETs is the traps in the channel.

823-mA/mm Drain Current Density and 945-MW/cm2 Baliga’s Figure-of-Merit Enhancement-Mode GaN MISFETs With a Novel PEALD-AlN/LPCVD-Si3N4 Dual-Gate Dielectric

In this letter, we demonstrate a novel PEALD-AlN/LPCVD-Si3N4 dual-gate dielectric employed in enhancement-mode GaN MISFETs, where the gate recess is fabricated based on our proposed self-terminating gate recess etching technique using a GaN cap layer as recess mask. By using LPCVD-Si3N4 and PEALD-AlN dual-gate dielectric layer, the devices exhibit a high-quality gate dielectric and a good GaN channel interface, yielding a high gate swing up to 18 V and a high channel effective mobility of 137 cm $^{\textsf {2}}/\textsf {V}\cdot \textsf {s}$ at such high gate bias. Thus, the fabricated devices feature a high maximum drain current density of 823mA/mm, a threshold voltage of 2.6 V, an on-resistance of $7.4~\Omega \cdot \textsf {mm}$ , and an ON/ OFF current ratio of 108 with gate–drain distance of $2~\mu \text{m}$ . Meanwhile, a high off-state breakdown voltage of 1290 V is achieved with 10- $\mu \text{m}$ gate–drain distance. The corresponding specific on-resistance is as low as 1.76 $\text{m}\Omega \cdot \textsf {cm}^{\textsf {2}}$ , leading to a high Baliga’s figure of merit of 945 MW/cm2.

Threshold voltage modulation mechanism of high-performance normally-off AlGaN/GaN gates-separating groove HFET

In this paper, we report on a novel enhancement-mode AlGaN/GaN gates-separating groove heterostructure field-effect transistor (GSG HFET), in which a block barrier exists between the double gates as realized by dry etching. The current transport dominated by thermionic emission or thermionic field emission results in a high drain current density. The threshold voltage modulation mechanism of AlGaN/GaN GSG HFET is investigated. Due to the increasing of block barrier height and width, the threshold voltage shifts obviously towards to the positive direction with increasing the gate length or gate-to-gate distance (Lgg). By optimizing the device structure, a threshold voltage of 1.8 V and a comparable drain current density of 550 mA/mm are obtained at Lgg = 180 nm, while the values of 2.5 V and 370 mA/mm are obtained at Lgg = 280 nm. Moreover, it's noteworthy that the threshold voltage is less sensitive to recess depth and etching time. The devices show high-uniformity threshold voltage within etching time range from 8 to 9 min.

High-Uniformity and High Drain Current Density Enhancement-Mode AlGaN/GaN Gates-Seperating Groove HFET

In this paper, we report on a novel E-mode AlGaN/GaN gates-seperating groove heterostructure field-effect transistor (GSG HFET). The current turn-on/off is controlled by changing gate voltage to regulate the horizontal energy band between the double gates. A threshold voltage of 0.23 V and a high drain current density of 851 mA/mm are obtained in GSG HFET. Compared with the proposed depletion-mode device, the maximum drain current of the GSG HFET deceases slightly (about 7%). It is noteworthy that the threshold voltage is less sensitive to the etching time. The devices show high-uniformity threshold voltage of 0.23 V within wide etching time range from 5 to 9 min.

β-Ga2O3 on insulator field-effect transistors with drain currents exceeding 1.5 A/mm and their self-heating effect

We have demonstrated that depletion/enhancement-mode β-Ga2O3 on insulator field-effect transistors can achieve a record high drain current density of 1.5/1.0 A/mm by utilizing a highly doped β-Ga2O3 nano-membrane as the channel. β-Ga2O3 on insulator field-effect transistor (GOOI FET) shows a high on/off ratio of 1010 and low subthreshold slope of 150 mV/dec even with 300 nm thick SiO2. The enhancement-mode GOOI FET is achieved through surface depletion. An ultra-fast, high resolution thermo-reflectance imaging technique is applied to study the self-heating effect by directly measuring the local surface temperature. High drain current, low Rc, and wide bandgap make the β-Ga2O3 on insulator field-effect transistor a promising candidate for future power electronics applications.

High-Performance GaN MOSHEMTs Fabricated With ALD Al2O3Dielectric and NBE Gate Recess Technology for High Frequency Power Applications

High-performance GaN metal–oxide–semi-conductor high-electron-mobility transistors (MOSHEMTs) using Al2O3 gate dielectric deposited by atomic layer deposition (ALD) and damage-free neutral beam etch (NBE) gate recess process for millimeter-wave power applications are demonstrated. The high-quality ALD Al2O3 reduces the gate leakage current of the device and the NBE method eliminates the plasma-induced defects in the nitride materials. The MOSHEMT device fabricated exhibits a high maximum drain current density ( ${I}_{\textsf {DS,max}}$ ) of 1.65 A/mm and a high peak extrinsic transconductance ( ${g}_{\textsf {m.ext}}$ ) of 653 mS/mm. The MOSHEMT device also demonstrates excellent RF performances, including ${f}_{T}/{f}_{\textsf {MAX}}= 183$ /191 GHz, NF $_{\textsf {min}}= 2.56$ dB with ${G}_{\textsf {AS}}= 5.61$ dB at 54 GHz, and an output power density of 2.7 W/mm associated with a power-added efficiency of 20.9% and a linear power gain of 9.4 dB at 38 GHz. To the best of our knowledge, the noise performance at 54 GHz is the best reported so far for the AlGaN/GaN HEMTs.

Impact of InGaN back barrier layer on performance of AIInN/AlN/GaN MOS-HEMTs

In the present work, we have discussed the effect of InGaN back barrier on device performances of 100 nm gate length AlInN/AlN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) device and a wide comparison is made with respect to without considering the back barrier layer. The InGaN layer is introduced in the intension to raise the conduction band of GaN buffer with respect to GaN channel so that there is an improvement in the carrier confinement and at the same time witnessed excellent high frequency performance. The simulations are carried out using 2D Sentaurus TCAD simulator using Hydrodynamic mobility model by taking interface traps into consideration. Due to high value of two-dimensional electron gas (2DEG) density and mobility in AlInN/AlN/GaN MOS-HEMT device, higher drain current density is achieved. Simulation are carried out for different device parameters such as transfer characteristic (Id-Vg), transconductance factor (gm), drain induced barrier lowering (DIBL), Subthreshold slope (SS), conduction band energy, transconductance generation factor (gm/Id) and electric field. We have also examined the RF performance such as, total gate capacitance (Cgg), current gain cutoff frequency (fT) and power gain cutoff frequency (fmax) of the proposed devices. Use of InGaN back barrier tends to increase threshold voltage towards more positive value, reduced DIBL, and improves SS and significant growth in (gm/Id) by 5.5%. It also helps to achieve better frequency response like substantial increase in fT up to 91 GHz with current gain 60 dB as compare to 67 GHz with 56 dB for the device without considering back barrier and increase in fmax up to 112 GHz with respect 94 GHz. These results evident that use of InGaN back barrier in such devices can be better solution for future analog and RF applications.