High Dielectric Films Research Articles

Suppressing the loss and enhancing the breakdown strengths of high-k materials via constructing layered structure

High dielectric materials are widely used in electronic devices, but their applications are severely hindered by the high loss and low breakdown strength. Herein, a layered structure is designed to effectively suppress the loss and enhance the breakdown strength of high dielectric materials. In the design, the high dielectric films are stacked with linear dielectric films, which can not only form breakdown barriers between adjacent layers but also reduce the leakage conduction loss. As a result, an obvious suppression of loss from 0.13 to 0.05 at 100 Hz, along with a significant increase of breakdown strength from 138 kV/mm to 413 kV/mm, are successfully achieved.

Portable Self-Powered Piezoelectric Nanogenerator and Self-Charging Photo-Power Pack Using In Situ Formed Multifunctional Calcium Phosphate Nanorod-Doped PVDF Films.

Herein, biocompatible Ca3(PO4)2 nanorod-incorporated poly(vinylidene) difluoride films have been prepared via an in situ process. A good piezoelectricity (d33 ≈ 56.6 pC/N) along with a large dielectric constant of ∼3.48 × 105 at frequency 20 Hz has been achieved. Then, we have designed a biocompatible, highly durable, low-cost piezoelectric nanogenerator (CPNG) which shows the superiority in open-circuit voltage ∼47 V and current ∼1.8 μA generation with power density ∼47.4 mW cm-3 under the gentle touch of a finger. Excellent mechanical to electrical energy conversion efficiency (∼65.5%) of our developed CPNG leads to fast charging of a capacitor of 1 μF in 18 s and glowing of 26 light-emitting diodes (LEDs) under finger impartation. Further, a portable light-charging power pack (LCPP) has been developed using the high dielectric film as the storage function. Under light illumination, our LCPP generates open-circuit output voltage ∼1.29 V with short-circuit current 5.7 mA cm-2. Areal capacitance ∼1779 F m-2 and storage efficiency ∼88% are achieved. The device is able to lighten up 22 LEDs for 10 days after charging once.

High dielectric permittivity and low dielectric loss in sol–gel derived Zn doped CaCu3Ti4O12 thin films

Zn-doped CaCu3−xZnxTi4O12 high dielectric films with low dielectric loss were prepared by the sol–gel method; their crystalline structure, microstructure and electrical properties were investigated. A new method, XRD complemented by CLSM, was used to prove the presence of ZnO in CCZTO films, indicating the existence of the Cu2+ vacancy which influenced the electrical properties directly. The average grain size enlarged with the increased Zn doping amounts. All the samples showed strong non-ohmic properties. Higher nonlinear coefficient and lower leakage current depended on the increased VCu″ concentration. It is significant that the Zn doping effectively reduced the dielectric loss in the low and medium frequency region even though the Zn doping led to the dielectric constant decreased compared to the pure CCTO film. At x = 0.20, the minimum dielectric loss of 0.015 can be observed around 22 000 Hz, which is the best-reported value in CCTO-based material.

Ultra-Compact WiMAX Bandpass Filter Embedded Into a Printed Circuit Board With a ${\rm SrTiO}_{3}$ Composite Layer

An ultra-compact bandpass filter has been developed for 2.3-2.7 GHz worldwide interoperability used for microwave access applications. The proposed filter was fully embedded into a multilayered printed circuit board (PCB) with a high dielectric strontium titanate (SrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) composite film layer. In order to reduce the size of the filter and to avoid unwanted 3-D electromagnetic coupling between the embedded passive filter circuit elements, the proposed filter was designed using J-inverter transformation technology. Two grounding via inductors and a single grounding capacitor were also utilized to generate three independent finite transmission zeros to enhance the rejection characteristics at the proper frequency bands. Since the J-inverter transformed filter circuit elements could be designed with relatively small inductance and large capacitance values, the high dielectric composite film was highly effective in reducing the size and improving the performance of the filter. The high dielectric film exhibited a dielectric constant of 17, a tangent loss of 0.01, and a capacitance density of 12.2 pF/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 1 GHz. The measured maximum insertion loss in the passband ranged from 2.3 to 2.7 GHz was better than 1.8 dB, with a minimum value of 1.58 dB at 2.6 GHz. The return loss was higher than 15 dB in the passband. The transmission zeros occurred at 1.71 and 5.1 GHz, and provided suppressions of 45 dB at 1.71 GHz, and 54 dB at 5.1 GHz, respectively. The measured group delay was less than 0.8 ns in the passband. The embedded bandpass filter had a volume of 2.6 × 2.6 × 0.55 (H) mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> , which is the smallest one found, compared to previously reported devices, the filter, embedded into the eight-layered packaging substrate with the high dielectric composite layer, dramatically reduced the size up to 56%, and its performance was also much improved in comparison to the one embedded into a conventional six- layered PCB.

Wideband LC balun transformer using coupled LC resonators embedded into organic substrate

In this paper, wideband LC balun using coupled LC resonator has been newly designed, simulated, and fabricated. The proposed balun has a novel scheme which consists of two pairs of coupled embedded LC resonators which share one resonator with each other. The coupled resonators are applied to provide a precise phase difference of 180° and an identical magnitude between two balanced ports and DC isolation characteristic with impedance transformation. Furthermore, proposed resonators have relatively small inductance values which can be easily embedded into the organic package substrate. In order to reduce the size of embedded capacitors, BTO composite high dielectric film was applied to increase their capacitance densities. The measured results of fabricated wideband balun exhibited an insertion loss of 1.8dB, a return loss of 10dB, a phase imbalance of 0.5°, and magnitude imbalance of 0.7dB at frequency bandwidth of 700MHz ranged from 1.8 to 2.5GHz, respectively. They agreed well with the simulated ones. The fabricated balun has a relatively small volume of 2mm×3.5mm×0.66mm (height).

Fully embedded lumped LC‐quadrature hybrid coupler into organic packaging substrate for power sampling

AbstractIn this article, fully embedded lumped LC‐quadrature hybrid coupler are designed, fabricated, and characterized into multilayered organic packaging substrate. This embedded device comprised high Q MIM capacitors and circular spiral stacked inductors. For realizing fully embedded high Q capacitor, barium titanate (BaTiO3) composite high dielectric film was utilized. The measured return loss and isolation were better than 25 dB. Measured insertion loss was about 0.38–0.42 dB at the frequencies ranged from 824 to 894 MHz. The coupler exhibited a coupling loss of 23.3–24 dB. The phase error between through and coupling ports was 1.2°–2.4°. It has a size of 2.8 mm ×2.95 mm ×0.77 mm (height), which is the smallest one in the couplers developed onto the packaging substrate. The measured performance characteristics were also well matched with the 3D EM simulated ones. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 845–848, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24173

Transient Capacitance in Metal-Oxide-Semiconductor Structures with Stacked Gate Dielectrics

Changes in transient capacitances during application of step voltages to the gate electrode of metal-oxide-semiconductor (MOS) structures with stacked gate dielectrics were investigated. The behaviors of the changes in transient capacitance varied depending on the thickness of high dielectric films. The results indicate that negative charges were trapped near the gate electrodes during stress voltage application, while positive charges were trapped near the Si/SiO2 interface. These charges in gate films were released at different time constants during relaxation.

A Study of Charge Control and Gate Tunneling in a Ferroelectric-Oxide-Silicon Field Effect Transistor

AbstractIt is known that conventional metal-oxide-silicon field-effect transistor (MOSFET) devices will have gate tunneling related problems at very thin oxide thicknesses (dox ≤ 20 Å). In this paper we discuss the potential of polar and non-polar high-dielectric films for gate tunneling suppression and charge control. We also examine ferroelectric thickness effects in ferroelectricoxide- silicon field effect transistors (MFISFETs). Our formalism is based on a blocking-layer model for the ferroelectric film and a self-consistent solution of the Poisson and Schrodinger equations. We show that the polarization effects of ferroelectrics can allow greater controllability of the silicon interface (mobile) charge density and also the high dielectric constant effectively suppresses gate tunneling probability. In addition, the effects of ferroelectric film thickness are quite important in a MFISFET device and allow a small control of the threshold voltage. Results will be presented for the capacitance-voltage curve, tunneling probability, and leakage currents. As an example, we find for a sheet charge of 1013 cm−2, the gate tunneling probability in a MOS structure is 10−6 (dox = 13 Å), while that in a MFISFET is 10−14 with the same equivalent oxide thickness. Our studies also show that details of the blocking layer model (dead layer thickness, coercive field, and polar charge) can be estimated from C-V measurements.

HIGH-DIELECTRIC CONSTANT THIN FILMS FOR DYNAMIC RANDOM ACCESS MEMORIES (DRAM)

▪ Abstract We discuss high-dielectric films, in general, oxide ferroelectrics based on simple perovskite structures and related Aurivillius-phase layered structure perovskites employed as thin-film capacitors in dynamic random access memories (DRAMs). Emphasis is on breakdown mechanisms and limits, leakage currents, electrodes and electrode interfaces, scaling to submicron geometries, and deposition techniques.

Etching of Platinum Thin Films by High Density Ar/Ci2/Hbr Plasma

ABSTRACTPlatinum is widely researched as the electrode material for capacitor of high dielectric films in dynamic random access memory (DRAM) application. However, the dry etching of Pt is difficult because of its chemical stability. So, the dry etching of Pt remains at the preliminary work.In this work, Pt etching mechanism was investigated by using inductive coupled plasma (ICP) with Ar/Cl2/HBr gas.The peaks were found due to brominated Pt as well as chlorinated Pt in the XPS (X-ray photoelectron spectroscopy) narrow scan. Ion bombardment effects on the etched surface decreased with increasing HBr/(HBr+Cl2) gas mixing ratio. The maximum etch rate of Pt was 105 nm/min at the HBr/(HBr+Cl2) ratio of 0. And selectivity to SiO2 was good in all samples with various HBr/(HBr+Cl2) gas mixing ratios. These results are consistent with XPS and OES (optical emission spectrometry) and single Langmuir probe.

Analysis of Overlay Accuracy in 0.14 µm Device Fabrication using Synchrotron Radiation Lithography

We applied synchrotron radiation lithography to the fabrication of a 0.14 µ m rule dynamic random access memory structure using high dielectric film capacitor and trench isolation techniques. An overlay accuracy of 80 nm was obtained. In order to clarify the contributions of the error causes to the overlay accuracy, we mathematically classified the overlay error into four components: rotation, translation, magnification and in-plane deformation (IPD). A rotation and translation error was estimated to be 38 nm. A wafer process-induced error such as a rotation and translation due to a degradation of the alignment mark worsens the overlay error by 33 nm. We have also found that the maximum magnification error including the mask magnification was 4 ppm and the magnification correction was necessary to achieve an overlay accuracy less than 50 nm. The IPD was estimated to be 60 nm, and the major cause was a mask overlay error. The analyzed results suggest that an IPD less than 30 nm and a rotation/translation component less than 30 nm are required to achieve an overlay error less than 50 nm.

A model of voltage-dependent dielectric losses for ferroelectric MMIC devices

Abstract The use of high-dielectric films for microwave devices, especially phased-array radar systems, in the tens of GHz regime requires very low-loss (0.01 to 0.1) films. Unfortunately most ferroelectrics have losses that diverge (greater than unity) in this frequency range. We develop in the present study quantitative models for dielectric loss in both SrTiO3 and BaxSr1−xTiO3 (BST) that give dependences upon temperature, frequency, and especially voltage or field. In pure strontium titanate we find that loss is intrinsic, with quality factor “Q” greater than 1000; and a dramatic voltage dependence of tan δ is observed to fit the C3/2(V) dependence upon capacitance predicted for three- and four-phonon anharmonicity for voltages up to 5V (E = 250 kV/cm). In most barium strontium titanate ceramic films the loss is extrinsic at 100 MHz, and the surface layer model of Neumann and Hofmann describes the dependence of tan δ upon thickness D rather well, with tan δ increasing from 0.001 at D = 5 microns to 0.10 at 50 nm. Typical values at 250 nm are ca. 0.015.

Electrode-dielectric interface in thin-film DRAMs for ULSI

Abstract Mechanisms of leakage currents and d.c. breakdown are reviewed for several high-dielectric films in prototype use for ULSI DRAMs, including barium strontium titanate, lead zirconate titanate, and proprietary materials, with special emphasis upon electrode interface phenomena. The early theory of Von Hippel is reviewed, and attention is paid to the modified boundary conditions to the thermal breakdown equation given below for the finite dimensions of capacitors in real ULSI DRAMs (EB is the breakdown field):