Abstract
Changes in transient capacitances during application of step voltages to the gate electrode of metal-oxide-semiconductor (MOS) structures with stacked gate dielectrics were investigated. The behaviors of the changes in transient capacitance varied depending on the thickness of high dielectric films. The results indicate that negative charges were trapped near the gate electrodes during stress voltage application, while positive charges were trapped near the Si/SiO2 interface. These charges in gate films were released at different time constants during relaxation.
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