Defect Generation in Ultrathin SiON / ZrO2 Gate Dielectric Stacks

Abstract

The generation of neutral defects and positive charge in ultrathin gate dielectric stacks during constant gate voltage stress of metal-oxide-semiconductor (MOS) capacitors is studied. A polarity dependence for the defect generation in these gate stacks is observed. It is shown that the anode-hole injection model is not adequate for explaining these results, but they can be explained by assuming the release of hydrogen close to the anode and its subsequent transport in the gate dielectric stack. The kinetics for defects generation can be quite well reproduced by a dispersive transport model, taking into account the random hopping of ions and their subsequent trapping in the gate dielectric stack. Comparing the data and the model, it is found that the positive charge is located close to the Si/SiON interface, while the neutral defect resides in the layer. © 2002 The Electrochemical Society. All rights reserved.